MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
CAUTION
These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such
as those experienced during reflow or hand soldering. See
for more information.
System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical
overstress or disturb of data or code memory. See the application report
MSP430™ System-Level ESD Considerations
CAUTION
DESCRIPTION
The Texas Instruments MSP430FR57xx family of ultralow-power microcontrollers consists of multiple devices
featuring embedded FRAM nonvolatile memory, ultralow power 16-bit MSP430 CPU, and different peripherals
targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power
modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a
new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash, all at lower total power consumption. Peripherals include 10-bit A/D converter, 16-channel
comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels
capable of I
2
C, SPI, or UART protocols, internal DMA, hardware multiplier, real-time clock, five 16-bit timers, and
more. The family members that are available are summarized in
Table 1. Family Members
eUSCI
Device
FRAM
(KB)
SRAM
(KB)
System
Clock
(MHz)
ADC10_B
Comp_D
Timer_A
(1)
Timer_B
(2)
Channel
A:
UART,
IrDA, SPI
2
Channel
B:
SPI, I
2
C
1
I/O
Package
MSP430FR5739
16
1
24
12 ext,
2 int ch.
6 ext, 2 int
ch.
16 ch.
10 ch.
12 ch.
9 ch.
16 ch.
10 ch.
3, 3
3, 3, 3
32
30
17
RHA
DA
RGE
PW
YFF
(3)
RHA
DA
RGE
PW
YFF
(3)
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
MSP430FR5738
16
1
24
8 ext, 2 int
ch.
5 ext, 2 int
ch.
3, 3
3
1
1
21
16
MSP430FR5737
16
1
24
3, 3
3, 3, 3
2
1
32
30
17
MSP430FR5736
16
1
24
12 ch.
9 ch.
3, 3
3
1
1
21
16
MSP430FR5735
8
1
24
12 ext,
2 int ch.
6 ext, 2 int
ch.
8 ext, 2 int
ch.
16 ch.
10 ch.
3, 3
3, 3, 3
2
1
32
30
17
MSP430FR5734
8
1
24
3, 3
12 ch.
16 ch.
10 ch.
12 ch.
3, 3
3
1
1
21
MSP430FR5733
8
1
24
3, 3, 3
2
1
32
30
17
21
32
30
MSP430FR5732
8
1
24
12 ext,
2 int ch.
3, 3
3
1
1
MSP430FR5731
4
1
24
16 ch.
3, 3
3, 3, 3
2
1
(1)
(2)
(3)
2
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
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