MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Table 1. Family Members (continued)
eUSCI
Device
FRAM
(KB)
SRAM
(KB)
System
Clock
(MHz)
ADC10_B
Comp_D
Timer_A
(1)
Timer_B
(2)
Channel
A:
UART,
IrDA, SPI
Channel
B:
SPI, I
2
C
I/O
Package
6 ext, 2 int
ch.
MSP430FR5730
4
1
24
8 ext, 2 int
ch.
5 ext, 2 int
ch.
MSP430FR5729
16
1
8
12 ext,
2 int ch.
6 ext, 2 int
ch.
8 ext, 2 int
ch.
10 ch.
12 ch.
9 ch.
16 ch.
10 ch.
3, 3
12 ch.
16 ch.
10 ch.
12 ch.
3, 3
3, 3, 3
2
1
3
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
17
21
16
32
30
17
21
32
30
17
21
32
30
17
3, 3
3
1
1
21
3, 3
3, 3, 3
2
1
32
30
17
21
32
30
17
3, 3
3
1
1
21
RGE
PW
YFF
(3)
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
RGE
PW
RHA
DA
RGE
PW
MSP430FR5728
16
1
8
MSP430FR5727
16
1
8
MSP430FR5726
16
1
8
12 ext,
2 int ch.
6 ext, 2 int
ch.
8 ext, 2 int
ch.
3, 3
3
1
1
MSP430FR5725
8
1
8
16 ch.
10 ch.
12 ch.
16 ch.
10 ch.
12 ch.
3, 3
3, 3, 3
2
1
MSP430FR5724
8
1
8
MSP430FR5723
8
1
8
MSP430FR5722
8
1
8
12 ext,
2 int ch.
6 ext, 2 int
ch.
8 ext, 2 int
ch.
3, 3
3
1
1
MSP430FR5721
4
1
8
16 ch.
10 ch.
12 ch.
3, 3
3, 3, 3
2
1
MSP430FR5720
4
1
8
Copyright © 2011–2012, Texas Instruments Incorporated
3
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