MSP430FR573x
MSP430FR572x
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Table 1. Family Members (continued)
eUSCI
System
Clock
(MHz)
Channel
Channel
FRAM
(KB)
SRAM
(KB)
Device
ADC10_B Comp_D Timer_A(1) Timer_B(2)
I/O
Package
A:
B:
UART,
IrDA, SPI
SPI, I2C
6 ext, 2 int
10 ch.
ch.
17
21
16
RGE
PW
8 ext, 2 int
MSP430FR5730
4
1
24
12 ch.
9 ch.
3, 3
3
1
1
ch.
5 ext, 2 int
ch.
YFF(3)
32
30
RHA
DA
12 ext,
2 int ch.
MSP430FR5729
MSP430FR5728
16
16
1
1
8
8
16 ch.
3, 3
3, 3
3, 3, 3
2
1
1
1
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
3
8 ext, 2 int
ch.
32
30
17
21
32
30
RHA
DA
MSP430FR5727
MSP430FR5726
MSP430FR5725
16
16
8
1
1
1
8
8
8
16 ch.
3, 3
3, 3
3, 3
3, 3, 3
3
2
1
2
1
1
1
10 ch.
12 ch.
RGE
PW
RHA
DA
12 ext,
2 int ch.
16 ch.
3, 3, 3
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
MSP430FR5724
8
1
8
3, 3
3
1
1
8 ext, 2 int
ch.
32
30
17
21
32
30
RHA
DA
MSP430FR5723
MSP430FR5722
MSP430FR5721
8
8
4
1
1
1
8
8
8
16 ch.
3, 3
3, 3
3, 3
3, 3, 3
3
2
1
2
1
1
1
10 ch.
12 ch.
RGE
PW
RHA
DA
12 ext,
2 int ch.
16 ch.
3, 3, 3
6 ext, 2 int
ch.
10 ch.
12 ch.
17
21
RGE
PW
MSP430FR5720
4
1
8
3, 3
3
1
1
8 ext, 2 int
ch.
Copyright © 2011–2012, Texas Instruments Incorporated
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