MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
TB0, TB1, TB2
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each. Each
can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 14. TB0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RHA
RGE, YFF
DA
PW
RHA
RGE, YFF
DA
PW
13-P2.0,
E5‑P2.0
21-P2.0
23-P2.0
19-P2.0
TB0CLK
TBCLK
ACLK
ACLK
(internal)
Timer
N/A
N/A
SMCLK
(internal)
SMCLK
TBCLK
13-P2.0,
E5‑P2.0
21-P2.0
23-P2.0
19-P2.0
TB0CLK
14-P2.1,
D3‑P2.1
14-P2.1,
D3‑P2.1
22-P2.1
17-P2.5
24-P2.1
19-P2.5
20-P2.1
15-P2.5
TB0.0
TB0.0
CCI0A
CCI0B
22-P2.1
17-P2.5
24-P2.1
19-P2.5
20-P2.1
15-P2.5
N/A
N/A
ADC10
(internal)
ADC10
(internal)
ADC10
(internal)
ADC10
(1)
CCR0
TB0
TB0.0
(1)
(1)
(1)
(internal)
DVSS
GND
ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {2}
= {2}
= {2}
= {2}
DVCC
VCC
5-P1.4,
B4‑P1.4
5-P1.4,
B4‑P1.4
9-P1.4
13-P1.4
9-P1.4
TB0.1
CCI1A
9-P1.4
13-P1.4
9-P1.4
ADC10
(internal)
ADC10
(internal)
ADC10
(internal)
ADC10
(1)
(1)
(1)
(1)
CDOUT
(internal)
(internal)
CCI1B
CCR1
TB1
TB0.1
ADC10SHSx ADC10SHSx ADC10SHSx ADC10SHSx
= {3}
= {3}
= {3}
= {3}
DVSS
DVCC
GND
VCC
6‑P1.5, A5-
P1.5
6-P1.5,
A5‑P1.5
10-P1.5
14-P1.5
19-P1.5
TB0.2
CCI2A
CCI2B
10-P1.5
14-P1.5
19-P1.5
ACLK
(internal)
CCR2
TB2
TB0.2
DVSS
DVCC
GND
VCC
(1) Only on devices with ADC
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
31
TI [ TEXAS INSTRUMENTS ]
