MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Table 18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
OFFSET
OFFSET
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
PMM Control 0
PMM interrupt flags
PM5 Control 0
00h
0Ah
10h
PMMIFG
PM5CTL0
Table 20. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
FRCTLCTL0
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
Table 21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
OFFSET
OFFSET
Watchdog timer control
00h
Table 23. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
00h
02h
04h
06h
08h
0Ah
0Ch
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
35
TI [ TEXAS INSTRUMENTS ]
