MSP430FR573x
MSP430FR572x
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SLAS639D –JULY 2011–REVISED AUGUST 2012
FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
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Low-power ultrafast write nonvolatile memory
Byte and word access capability
Programmable and automated wait state generation
Error Correction Coding (ECC) with single bit detection and correction, double bit detection
Memory Protection Unit (MPU)
The FRAM can be protected from inadvertent CPU execution or write access by the MPU. Features of the MPU
include:
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Main memory partitioning programmable up to three segments
Each segment's (main and information memory) access rights can be individually selected
Access violation flags with interrupt capability for easy servicing of access violations
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430FR57xx Family User's Guide (SLAU272).
Digital I/O
There are up to four 8-bit I/O ports implemented:
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All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF mode), an internal very-low-
power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a high-
frequency crystal oscillator XT1 (HF mode). The clock system module is designed to meet the requirements of
both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock
system module provides the following clock signals:
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Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1 LF mode), a high-frequency crystal (XT1
HF mode), the internal VLO, or the internal DCO.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by the same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
the same sources made available to ACLK.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also
includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit is implemented to
provide the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if
the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the primary and core
supplies.
Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations.
Copyright © 2011–2012, Texas Instruments Incorporated
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