MSP430FR573x
MSP430FR572x
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SLAS639D –JULY 2011–REVISED AUGUST 2012
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up, Brownout, Supply
Supervisors
SVSLIFG, SVSHIFG
PMMRSTIFG
External Reset RST
WDTIFG
Watchdog Timeout (Watchdog
mode)
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
DBDIFG
Reset
0FFFEh
63, highest
WDT, FRCTL MPU, CS, PMM
Password Violation
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
FRAM double bit error detection
MPU segment violation
Software POR, BOR
PMMPORIFG, PMMBORIFG
(1) (2)
(SYSRSTIV)
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
Access violation
VMAIFG
JMBNIFG, JMBOUTIFG
ACCTIMIFG
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
ACCVIFG
SBDIFG, DBDIFG
FRAM single, double bit error
detection
(1)
(SYSSNIV)
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV)
(1) (2)
Comparator_D interrupt flags
Comparator_D
TB0
Maskable
Maskable
0FFF8h
0FFF6h
60
59
(1) (3)
(CBIV)
(3)
TB0CCR0 CCIFG0
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0IFG
TB0
Maskable
Maskable
0FFF4h
0FFF2h
58
57
(1) (3)
(TB0IV)
Watchdog Timer
(Interval Timer Mode)
WDTIFG
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
UXA0TXIFG (UART mode)
eUSCI_A0 Receive and Transmit
eUSCI_B0 Receive and Transmit
ADC10_B
Maskable
Maskable
Maskable
0FFF0h
0FFEEh
0FFECh
56
55
54
(1) (3)
(UCA0IV)
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(1) (3)
(UCB0IV)
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10INIFG, ADC10IFG0
(1) (3) (4)
(ADC10IV)
(3)
TA0
TA0
TA0CCR0 CCIFG0
Maskable
Maskable
0FFEAh
0FFE8h
53
52
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0IFG
(1) (3)
(TA0IV)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved.
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