MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Table 5. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
UXA1TXIFG (UART mode)
eUSCI_A1 Receive and Transmit
Maskable
0FFE6h
51
(1) (3)
(UCA1IV)
DMA0IFG, DMA1IFG, DMA2IFG
DMA
TA1
Maskable
Maskable
0FFE4h
0FFE2h
50
49
(1) (3)
(DMAIV)
(3)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG
TA1
Maskable
0FFE0h
48
(1) (3)
(TA1IV)
P1IFG.0 to P1IFG.7
I/O Port P1
TB1
Maskable
Maskable
0FFDEh
0FFDCh
47
46
(1) (3)
(P1IV)
(3)
TB1CCR0 CCIFG0
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1IFG
TB1
Maskable
0FFDAh
45
(1) (3)
(TB1IV)
P2IFG.0 to P2IFG.7
I/O Port P2
TB2
Maskable
Maskable
0FFD8h
0FFD6h
44
43
(1) (3)
(P2IV)
(3)
TB2CCR0 CCIFG0
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2IFG
TB2
Maskable
0FFD4h
42
(1) (3)
(TB2IV)
P3IFG.0 to P3IFG.7
I/O Port P3
I/O Port P4
Maskable
Maskable
0FFD2h
0FFD0h
41
40
(5) (6)
(P3IV)
P4IFG.0 to P4IFG.2
(5) (6)
(P4IV)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
RTC_B
Maskable
0FFCEh
39
(5) (6)
(RTCIV)
0FFCCh
⋮
38
(7)
Reserved
Reserved
⋮
0FF80h
0, lowest
(5) Multiple source flags
(6) Interrupt flags are located in the module.
(7) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
22
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