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HPC3130APBMQUADFLAT 参数 Datasheet PDF下载

HPC3130APBMQUADFLAT图片预览
型号: HPC3130APBMQUADFLAT
PDF下载: 下载PDF文件 查看货源
内容描述: PCI热插拔控制器 [PCI HOT PLUG CONTROLLER]
分类和应用: 控制器PC
文件页数/大小: 41 页 / 537 K
品牌: TI [ TEXAS INSTRUMENTS ]
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HPC3130A  
PCI HOT PLUG CONTROLLER  
SCPS055 – NOVEMBER 1999  
configuration and control registers (continued)  
hot-plug slot control register  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Default  
Hot-plug slot control register  
R
0
R
0
R/W  
1
R/W  
0
R/W  
1
R/W  
1
R/W  
0
R/W  
1
Register:  
Type:  
Hot-plug slot control  
Read-only, Read/Write  
Offset:  
Default:  
Description:  
02 (slot 0), 0Ah (slot 1), 12h (slot 2), 1Ah (slot 3)  
2Dh  
This register applies power, resets, and provides general control of a hot-plug slot  
connection to the system PCI bus.  
Table 10. Hot-Plug Slot Control Register  
BIT  
7
TYPE  
NAME  
FUNCTION  
Reserved. This bit returns 0 when read.  
R
R
RSVD  
RSVD  
6
Reserved. This bit returns 0 when read.  
Slot power On/Off control. The data written to this bit represents the logical value of the data to drive the  
PWRON/OFF output and is used to control the power state of a hot-plug slot. If the PROTECTEN bit in the  
general configuration register is set to 1, then a logic high can only be driven by the PWRON/OFF output if  
the DETECT[1:0] inputs are low.  
5
R/W  
SLTPWR_CTL  
PCI bus CBT-switch control. When manual sequencing is enabled, then the value written to this bit  
represents the logical value of the data driven to the BUSON output, and it is used to connect/disconnect a  
hot-plug slot to/from the PCI bus.  
Ifanautosequencingmodeisenabledinthegeneralconfigurationregister, thenthisbitfunctionsasfollows:  
1 = By setting this bit, the hot-plug slot gets disconnected from the PCI bus. This is accomplished by  
asserting IDLEREQ, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY  
before driving BUSON high, CLKON high, REQ64ON low, and PWRON/OFF low.  
0 = By clearing this bit, the hot-plug slot gets connected to the PCI bus. This is accomplished by asserting  
IDLEREQ, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY before driving  
BUSON low. Also verifies assertion of DETECT[1:0] if the protection enable bit is enabled in the  
general configuration register.  
4
3
R/W  
R/W  
BUS_CTL  
Slot request 64-bit control. The data written to this bit represents the logical value of the data driven to the  
SLOTREQ64 SLOTREQ64output and is used during reset of a slot after power is applied. This input indicates to anoption  
card whether or not it is connected to a 64-bit slot.  
REQ64 CBT switch control. The data written to this bit represents the logical value of the data driven to the  
REQ64_O  
2
1
0
R/W  
R/W  
R/W  
REQ64ON output and is used to control the CBT switch that implements the REQ64 PCI signal.  
CLKON CBT switch control. The data written to this bit represents the logical value of the data driven to the  
CLKON output and is used to control the clock driver to the hot-plug slot.  
CLKON_O  
Slot reset control. The data written to this bit represents the logical value of the data driven to the SLOTRST  
output and is used to reset a hot-plug slot after power is applied.  
SLOTRST_O  
28  
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