HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
interrupt event enable register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt event enable register
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Interrupt event enable
Read-only, Read/Write
Offset:
Default:
Description:
07h (slot 0), 0Fh (slot 1), 17h (slot 2), 1Fh (slot 3)
00h
This register is used to enable interrupts, signaled through the open-drain INTR, after
detecting various events. Event status is reported through the interrupt event status
register.
Table 13. Interrupt Event Enable Register
BIT
TYPE
NAME
FUNCTION
7
R
RSVD
Reserved. This bit returns 0 when read.
PCI bus CBT switch event enable. When this bit is set, an INTR is signaled when the BUSON output
changes state. The BUS event is intended for use with the idling protocol.
6
5
R/W
BUS_E
Powergoodeventenable. Whenthisbitisset, anINTRissignaledwhenthePWRGOODinputchanges
state.
R/W
PWRGOOD_E
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
PWRFAULT_E Power fault event enable. When this bit is set, an INTR is signaled when PWRFAULT input is asserted.
DETECT1_E
DETECT0_E
PRSNT2_E
PRSNT1_E
Mechanical detect 1 event enable. Enables INTR events on DETECT1 input state changes.
Mechanical detect 0 event enable. Enables INTR events on DETECT0 input state changes.
Card present 2 event enable. Enables INTR events on PRSNT2 input state changes.
Card present 1 event enable. Enables INTR events on PRSNT1 input state changes.
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