HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers
The HPC3130A register set is accessible through either a generic parallel bus interface or a two-wire serial
interface. Eight bytes of register space are provided per slot. Since the HPC3130A supports four slots, a total
of 32 bytes of registers is implemented. Register and bit descriptions are provided in the following sections and
indicate the bits that are common to all slots. The bit default values are given, which represent the state of the
HPC3130A after a PCI reset event. After a PCI reset, the HPC3130A drives outputs to a state such that the slots
appear as if they were not a hot-plug platform.
The register map that follows provides the register overview. Byte addressing is required when accessing the
internal registers. Read transactions from reserved registers return zeros.
Table 7. Register Map
SLOT
Slot 0
Slot 0
Slot 0
Slot 0
Slot 0
Slot 0
Slot 0
Slot 0
Slot 1
Slot 1
Slot 1
Slot 1
Slot 1
Slot 1
Slot 1
Slot 1
REGISTER NAME
General configuration register
Hot-plug slot status register
Hot-plug slot control register
Attention indicator control
Reserved
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
SLOT
Slot 2
Slot 2
Slot 2
Slot 2
Slot 2
Slot 2
Slot 2
Slot 2
Slot 3
Slot 3
Slot 3
Slot 3
Slot 3
Slot 3
Slot 3
Slot 3
REGISTER NAME
General configuration register
Hot-plug slot status register
Hot-plug slot control register
Attention indicator control
Reserved
ADDRESS
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Reserved
Reserved
Interrupt event status register
Interrupt event enable register
General configuration register
Hot-plug slot status register
Hot-plug slot control register
Attention indicator control
Reserved
Interrupt event status register
Interrupt event enable register
General configuration register
Hot-plug slot status register
Hot-plug slot control register
Attention indicator control
Reserved
Reserved
Reserved
Interrupt event status register
Interrupt event enable register
Interrupt event status register
Interrupt event enable register
25
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