HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
general configuration register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
General configuration register
R
0
R
0
R
1
R
1
R/W
0
R/W
0
R
X
R/W
0
Register:
Type:
General configuration
Read-only, Read/Write
Offset:
Default:
Description:
00h (slot 0), 08h (slot 1), 10h (slot 2), 18h (slot 3)
0Xh
This register is for general configurations and indications. The automatic PCI bus
connection sequencing is enabled through this register, and the register access mode is
indicated. This register is shared among all four slots.
Table 8. General Configuration Register
BIT
TYPE
NAME
RSVD
FUNCTION
7–4
R
Reserved for revision ID. These bits return 0011b for this device.
Automatic PCI bus connection sequencing. These bits control the sequencing used to connect the hot-
plug slot to the PCI bus.
00 = Manual sequencing through register accesses
01 = Auto–Sequence 1: Enable CBT switches before deasserting RST
10 = Auto–Sequence 2: Enable CBT switches after deasserting RST
11 = Reserved
3–2
R/W
SEQUENCING
StatusofSYSM66EN.ThisbitrepresentsthelatchedvalueofSYSM66ENduringaPCIreset.Avalueof
1
0
R
SYSM66STAT 1 indicates the PCI bus is operating at a frequency greater than 33 MHz. A value of 0 indicates the PCI
bus is operating at 33 MHz or less.
Protectionenable.ThisbitenablesaprotectionmechanismprovidedbytheHPC3130A.Whenthisbitis
R/W
PROTECTEN
enabledandeitheroftheDETECT[1:0]inputsarehigh,theHPC3130AdrivestheBUS_ONandCLKON
outputs high. The HPC3130A also drives PWRON/OFF and REQ64ON outputs low.
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