HPC3130A
PCI HOT PLUG CONTROLLER
SCPS055 – NOVEMBER 1999
configuration and control registers (continued)
interrupt event status register
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Interrupt event status register
R
0
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
R/C
0
Register:
Type:
Interrupt event status
Read-only, Read/Clear
Offset:
Default:
Description:
06h (slot 0), 0Eh (slot 1), 16h (slot 2), 1Eh (slot 3)
00h
This register reads interrupt status, and clears the interrupt. All functional bits in this
register are readable and cleared by a write back of 1. The HPC3130A can be programmed
to generate an interrupt, signaled through the open-drain INTR, after detecting various
events. Each event is individually enabled through the interrupt event enable register.
Table 12. Interrupt Event Status Register
BIT
TYPE
NAME
FUNCTION
7
R
RSVD
Reserved. This bit returns 0 when read.
PCI Bus CBT switch status. This bit is set when the BUSON output changes state, and is cleared by a
write back of 1. The BUS event is intended for use with the idling protocol.
6
R/C
BUS_S
5
4
3
2
1
0
R/C
R/C
R/C
R/C
R/C
R/C
PWRGOOD_S Power good status. This bit is set when the PWRGOOD input changes state.
PWRFAULT_S Power fault status. This bit is set when the PWRFAULT input is asserted.
DETECT1_S
DETECT0_S
PRSNT2_S
PRSNT1_S
Mechanical detect 1 status. This bit is set when the DETECT1 input changes state.
Mechanical detect 0 status. This bit is set when the DETECT0 input changes state.
Card present 2 status. This bit is set when the PRSNT2 input changes state.
Card present 1 status. This bit is set when the PRSNT1 input changes state.
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