3.0 Functional Description (Continued)
Table II. 4B5B code-group Encoding/Decoding.
PCS 5B Code-group MII 4B Nibble Code
Name
DATA CODES
0
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IDLE AND CONTROL CODES
H
00100
11111
11000
10001
01101
00111
Halt code-group - Error code
I
Inter-Packet Idle - 0000*
J
First Start of Packet - 0101*
Second Start of Packet - 0101*
First End of Packet - 0000*
Second End of Packet - 0000*
K
T
R
INVALID CODES
V
V
V
V
V
V
V
V
V
V
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
0110 or 0101*
*Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
**Normally, invalid codes (V) are mapped to 6h on RXD[3:0] with RX_ER asserted. If the CODE_ERR bit in the LBREMR (bit 4, register address 18h) is
set, the invalid codes are mapped to 5h on RXD[3:0] with RX_ER asserted. Refer to section 4.14 for further detail.
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