DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Table 3-16. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions (continued)
SIGNAL NAME [1]
DDR[0]_D[21]
DESCRIPTION [2]
TYPE [3]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
AAR BALL [4]
AG16
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0]_D[22]
DDR[0]_D[23]
DDR[0]_D[24]
DDR[0]_D[25]
DDR[0]_D[26]
DDR[0]_D[27]
DDR[0]_D[28]
DDR[0]_D[29]
DDR[0]_D[30]
DDR[0]_D[31]
DDR[0]_DQM[0]
DDR[0]_DQM[1]
DDR[0]_DQM[2]
DDR[0]_DQM[3]
DDR[0]_DQS[0]
DDR[0]_DQS[0]
AD16
AC16
AK19
AJ19
AH19
AF19
AD19
AC19
AJ20
AG20
AL8
Data Mask for lower byte data bus DDR[0]_D[7:0]
Data Mask for DDR[0]_D[15:8]
O
AK12
AJ15
AK18
AL11
AK11
Data Mask for DDR[0]_D[23:16]
O
Data Mask for upper byte data bus DDR[0]_D[31:24]
Data Strobe for lower byte data bus DDR[0]_D[7:0]
O
I/O
I/O
Complimentary data strobe for lower byte data bus
DDR[0]_D[7:0]
DDR[0]_DQS[1]
DDR[0]_DQS[1]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
DDR[0]_DQS[3]
Complimentary data strobe for DDR[0]_D[15:8]
Data Strobe for DDR[0]_D[15:8]
I/O
I/O
I/O
I/O
I/O
AK15
AL15
AL17
AK17
AK20
Data Strobe for DDR[0]_D[23:16]
Complimentary data strobe for DDR[0]_D[23:16]
Complimentary data strobe for upper byte data bus
DDR[0]_D[31:24]
DDR[0]_DQS[3]
DDR[0]_ODT[0]
DDR[0]_RAS
DDR[0]_RST
DDR[0]_VTP
DDR[0]_WE
Data Strobe for upper byte data bus DDR[0]_D[31:24]
DDR[0] On-Die Termination for Chip Select 0
DDR[0] Row Address Strobe output
DDR[0] Reset output
I/O
O
O
O
I
AL20
AL21
AJ25
AA20
AL30
AL26
DDR VTP Compensation Resistor Connection
DDR[0] Write Enable
O
70
Device Pins
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