DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
3.3.7 EMAC [(R)(G)MII Modes] and MDIO
3.3.7.1 EMAC
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Table 3-18. EMAC Terminal Functions [(R)(G)MII]
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
AL6
EMAC[0]_GMTCLK/EMAC[1]_RGRXC
GMII Source Asynchronous Transmit Clock / RGMII
Receive Clock
I/O
EMAC[0]_MCOL/EMAC[0]_RGRXCTL
[G]MII Collision Detect (Sense) input / RGMII Receive
Control
I
AH1
EMAC[0]_MCRS/EMAC[0]_RGRXD[2]
EMAC[0]_MRCLK/EMAC[0]_RGTXC
EMAC[0]_MRXDV/EMAC[1]_RGRXD[1]
EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0]
EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0]
EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1]
EMAC[0]_MRXD[3]/EMAC[1]_RGRXCTL
EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3]
EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3]
EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2]
EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1]
EMAC[0]_MRXER/EMAC[0]_RGTXCTL
EMAC[0]_MTCLK/EMAC[0]_RGRXC
EMAC[0]_MTXD[0]/EMAC[1]_RGRXD[3]
EMAC[0]_MTXD[1]/EMAC[1]_RGTXD[1]
EMAC[0]_MTXD[2]/EMAC[1]_RGTXCTL
EMAC[0]_MTXD[3]/EMAC[1]_RGTXD[0]
EMAC[0]_MTXD[4]/EMAC[1]_RGTXD[2]
EMAC[0]_MTXD[5]/EMAC[1]_RGTXC
EMAC[0]_MTXD[6]/EMAC[1]_RGRXD[0]
EMAC[0]_MTXD[7]/EMAC[1]_RGTXD[3]
EMAC[0]_MTXEN/EMAC[1]_RGRXD[2]
[G]MII Carrier Sense input / RGMII Receive Data
[G]MII Receive Clock / RGMII Transmit Clock
[G]MII Receive Data Valid input / RGMII Receive Data
[G]MII Receive Data / RGMII Transmit Data
[G]MII Receive Data / RGMII Receive Data
[G]MII Receive Data / RGMII Receive Data
[G]MII Receive Data / RGMII Receive Control
[G]MII Receive Data / RGMII Receive Data
[G]MII Receive Data / RGMII Transmit Data
[G]MII Receive Data / RGMII Transmit Data
[G]MII Receive Data / RGMII Transmit Data
I
AH2
AK1
AJ6
AK2
AL2
AL3
AK3
AK4
AJ4
AL5
AK5
AJ2
AG4
AK6
AJ7
AK7
AE4
AK8
AJ8
AH8
AG8
AF8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[G]MII Receive Data Error input / RGMII Transmit Enable I/O
[G]MII Transmit Clock input / RGMII Receive Clock
[G]MII Transmit Data / RGMII Receive Data
[G]MII Transmit Data / RGMII Transmit Data
[G]MII Transmit Data / RGMII Trasmit Enable
[G]MII Transmit Data / RGMII Transmit Data
[G]MII Transmit Data / RGMII Transmit Data
[G]MII Transmit Data / RGMII Transmit Clock
[G]MII Transmit Data / RGMII Receive Data
[G]MII Transmit Data / RGMII Transmit Data
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[G]MII Transmit Data Enable output / RGMII Receive
Data
EMAC[0]_RMCRSDV
EMAC[0]_RMRXD[0]
EMAC[0]_RMRXD[1]
EMAC[0]_RMRXER
EMAC[0]_RMTXD[0]
EMAC[0]_RMTXD[1]
EMAC[0]_RMTXEN
EMAC[1]_GMTCLK
EMAC[1]_MCOL
RMII Carrier Sense input
RMII Receive Data
I
AK1
AH1
AH2
AJ2
AK2
AL2
AL3
H4
I
RMII Receive Data
I
RMII Receive Data Error input
RMII Transmit Data
I
O
O
O
O
I
RMII Transmit Data
RMII Transmit Data Enable output
GMII Source Asynchronous Transmit Clock
[G]MII Collision Detect (Sense) input
[G]MII Carrier Sense input
[G]MII Receive Clock
E2
EMAC[1]_MCRS
I
F5
EMAC[1]_MRCLK
EMAC[1]_MRXD[0]
EMAC[1]_MRXD[1]
EMAC[1]_MRXD[2]
EMAC[1]_MRXD[3]
EMAC[1]_MRXD[4]
EMAC[1]_MRXD[5]
EMAC[1]_MRXD[6]
I
F2
[G]MII Receive Data
I
F3
[G]MII Receive Data
I
G1
[G]MII Receive Data
I
G2
[G]MII Receive Data
I
H3
[G]MII Receive Data
I
G3
[G]MII Receive Data
I
H5
[G]MII Receive Data
I
H6
72
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