DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
3.3.5 DDR2/DDR3/DDR3L Memory Controller
Table 3-16. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
DDR[0] Address Bus
TYPE [3]
O
AAR BALL [4]
AL24
DDR[0]_A[0]
DDR[0]_A[1]
DDR[0]_A[2]
DDR[0]_A[3]
DDR[0]_A[4]
DDR[0]_A[5]
DDR[0]_A[6]
DDR[0]_A[7]
DDR[0]_A[8]
DDR[0]_A[9]
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Address Bus
DDR[0] Bank Address outputs
DDR[0] Bank Address outputs
DDR[0] Bank Address outputs
DDR[0] Column Address Strobe output
DDR[0] Clock Enable
DDR[0] Negative Clock
DDR[0] Clock
O
AC22
AJ23
AJ27
AK28
AH27
AK30
AG23
AL29
AK29
AD23
AK24
AH23
AK23
AL23
AK22
AK26
AF23
AH25
AK25
AD20
AK27
AL27
AB21
AL9
O
O
O
O
O
O
O
O
DDR[0]_A[10]
DDR[0]_A[11]
DDR[0]_A[12]
DDR[0]_A[13]
DDR[0]_A[14]
DDR[0]_A[15]
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
DDR[0]_CAS
DDR[0]_CKE
DDR[0]_CLK
DDR[0]_CLK
DDR[0]_CS[0]
DDR[0]_D[0]
DDR[0]_D[1]
DDR[0]_D[2]
DDR[0]_D[3]
DDR[0]_D[4]
DDR[0]_D[5]
DDR[0]_D[6]
DDR[0]_D[7]
DDR[0]_D[8]
DDR[0]_D[9]
DDR[0]_D[10]
DDR[0]_D[11]
DDR[0]_D[12]
DDR[0]_D[13]
DDR[0]_D[14]
DDR[0]_D[15]
DDR[0]_D[16]
DDR[0]_D[17]
DDR[0]_D[18]
DDR[0]_D[19]
DDR[0]_D[20]
O
O
O
O
O
O
O
O
O
O
O
O
O
DDR[0] Chip Select
DDR[0] Data Bus
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDR[0] Data Bus
AK9
DDR[0] Data Bus
AK10
AJ11
AH11
AD9
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
AF11
AL12
AJ12
AG12
AD12
AB12
AK13
AC13
AL14
AK14
AH15
AF15
AD15
AK16
AJ16
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
DDR[0] Data Bus
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