DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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Processor
DQS
DDR
DQSn+
DQSn-
DQS
IO Buffer
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
Figure 8-76. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
Dn
DQ and DM
IO Buffer
n = 0, 1, 2, 3
Figure 8-77. DQ/DM Topology
8.13.3.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-78 and Figure 8-79 show the DQS and DQ/DM routing.
DQS
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2, 3
Figure 8-78. DQS Routing With Any Number of Allowed DDR3 Devices
DQ and DM
Dn
n = 0, 1, 2, 3
Figure 8-79. DQ/DM Routing With Any Number of Allowed DDR3 Devices
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Peripheral Information and Timings
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