DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
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DDR Differential CK Input Buffer
–
+
Clock Parallel
Terminator
DVDD_DDR[0]
Rcp
A1
A1
A2
A2
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
Figure 8-72. CK Topology for One DDR3 Device
DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
AT
Vtt
Figure 8-73. ADDR_CTRL Topology for One DDR3 Device
8.13.3.14.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
Figure 8-74 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-75
shows the corresponding ADDR_CTRL routing.
244
Peripheral Information and Timings
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