DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
Recommended Operating Conditions (continued)
PARAMETER
MIN
NOM
MAX UNIT
High-level input voltage, LVCMOS (JTAG[TCK] pins), 3.3
V(2)
2
V
High-level input voltage, JTAG[TCK], 3.3 V
High-level input voltage, JTAG[TCK], 1.8 V
High-level input voltage, I2C (I2C[0] and I2C[1])
2.15
1.45
V
V
V
V
0.7DVDD
0.65DVDDx
High-level input voltage, LVCMOS(2), 1.8 V
VIH
High-level input voltage, DDR[0] signals in DDR2 mode
High-level input voltage, DDR[0] signals in DDR3 mode
High-level input voltage, DDR[0] signals in DDR3L mode
VREFSSTL_DDR[x]
+ 0.125
V
V
V
VREFSSTL_DDR[x]
+ 0.1
VREFSSTL_DDR[x]
+ 0.09
Low-level input voltage, LVCMOS(2), 3.3 V
Low-level input voltage, JTAG[TCK]
0.8
0.45
V
V
V
V
Low-level input voltage, I2C (I2C[0] and I2C[1])
Low-level input voltage, LVCMOS(2), 1.8 V
0.3DVDDx
0.35DVDDx
Low-level input voltage, DDR[0] signals in DDR2 mode
Low-level input voltage, DDR[0] signals in DDR3 mode
Low-level input voltage, DDR[0] signals in DDR3L mode
VREFSSTL_DDR[x]
- 0.125
VIL
V
V
V
VREFSSTL_DDR[x]
- 0.1
VREFSSTL_DDR[x]
- 0.09
High-level output current
Low-level output current
6 mA I/O buffers
-6 mA
-8 mA
IOH
DDR[0] buffer @ 50-Ω
impedance setting
6 mA I/O buffers
6
8
mA
mA
V
IOL
VID
tt
DDR[0] buffer @ 50-Ω
impedance setting
Differential input voltage (SERDES_CLKN/P), [AC coupled]
0.250
2.0
Transition time, 10% - 90%, All inputs (unless otherwise
specified in the Electrical Data/Timing sections of each
peripheral)
0.25P or 10(4)
ns
Operating junction temperature
range(5)
Commercial
Temperature (default)
TJ
0
95
95
°C
°C
Extended temperature
-40
(4) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
(5) For more detailed information on estimating junction temps within systems, see the IC Package Thermal Metrics Application Report
(Literature Number: SPRA953).
Copyright © 2013, Texas Instruments Incorporated
Device Operating Conditions
125
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