DM385 参数 Datasheet PDF下载

型号：	DM385
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内容描述：	DM385和DM388 DaVincia ？ ¢数字媒体处理器 [DM385 and DM388 DaVinciâ¢ Digital Media Processor]
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文件页数/大小：	280 页 / 2479 K
品牌：	TI [ TEXAS INSTRUMENTS ]

DM385, DM388

www.ti.com

SPRS821D –MARCH 2013–REVISED DECEMBER 2013

The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large

number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to

four initiators and can distribute those communication requests to and collect related responses from up to

63 targets.

The device provides two interfaces with L3 interconnect for high-speed and standard peripherals.

Table 5-2. L4 Peripheral Connectivity⁽¹⁾

MASTERS

L4 PERIPHERALS

ARM Cortex-A8

M2 (64-bit)

EDMA TPTC0 EDMA TPTC1 EDMA TPTC2 EDMA TPTC3

PCIe

L4 Fast Peripherals Port 0/1

EMAC SW

L4 Slow Peripherals Port 0/1

I2C0

Port0

Port1

Port0

Port1

Port0

Port1

Port0

Port1

Port0

Port1

Port0

Port1

I2C1

I2C2

I2C3

SPI0

SPI1

SPI2

SPI3

UART0

UART1

UART2

Timer1

Timer2

Timer3

Timer4

Timer5

Timer6

Timer7

Timer8

GPIO0

GPIO1

MMC/SD0/SDIO

MMC/SD1/SDIO

MMC/SD2/SDIO

WDT0

RTC

SmartReflex0

SmartReflex1

Mailbox

Spinlock

HDVPSS

PLLSS

Port1

Port0

Port1

Port0

Port1

Control/Top Regs (Control

Module)

PRCM

ELM

Port0

Port1

(1) X, Port0, Port1 = Connection exists.

System Interconnect

121

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