DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
7 Power, Reset, Clocking, and Interrupts
7.1 Power, Reset and Clock Management (PRCM) Module
The PRCM module is the centralized management module for the power, reset, and clock control signals
of the device. It interfaces with all the components on the device for power, clock, and reset management
through power-control signals. It integrates enhanced features to allow the device to adapt energy
consumption dynamically, according to changing application and performance requirements. The
innovative hardware architecture allows a substantial reduction in leakage current.
The PRCM module is composed of two main entities:
•
Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock
source control (oscillator)
•
Clock manager (CM): Handles the clock generation, distribution, and management.
For more details on the PRCM, see the Power, Reset, and Clock Management (PRCM) Module chapter in
the device-specific Technical Reference Manual.
7.2 Power
7.2.1 Voltage and Power Domains
Every Module within the device belongs to a Core Logic Voltage Domain, Memory Voltage Domain, and a
Power Domain (see Table 7-1).
Table 7-1. Voltage and Power Domains
CORE LOGIC
VOLTAGE DOMAIN
MEMORY VOLTAGE
DOMAIN
POWER
DOMAIN
MODULE(S)
ARM_L
ARM_M
ARM Cortex-A8 Subsystem, SmartReflex Sensor 0
ATL, HDMI, DMM, EDMA, ELM, DDR, EMAC Switch,
GPIO Banks 0/1/2/3, GPMC, I2C0/1/2/3, IPC,
MCASP0/1, OCMC SRAM, PCIE, PRCM, RTC,
SD/MMC0/1/2, SPI01/2/3, Timer1/2/3/4/5/6/7/8,
UART0/1/2, USB0/1, WDT0, System Interconnect,
JTAG, Media Controller, ISS, SmartReflex Control
Module 0/1, SmartReflex Sensor 1
ALWAYS ON
CORE_L
CORE_M
ISP
ISP, CSI2 PHY LOGIC
HDVPSS
HDVICP
HDVPSS, SD-DAC, HD-DAC
HDVICP2, SmartReflex Sensor 2
HDVICP_L
HDVICP_M
7.2.1.1 Core Logic Voltage Domains
The device contains three Core Logic Voltage Domains. These domains define groups of Modules that
share the same supply voltage for their core logic. Each Core Logic Voltage Domain is powered by a
dedicated supply voltage rail that can be independently scaled using SmartReflex technology to trade off
power versus performance. Table 7-2 shows the mapping between the Core Logic Voltage Domains and
their associated supply pins.
Copyright © 2013, Texas Instruments Incorporated
Power, Reset, Clocking, and Interrupts
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