DM385, DM388
SPRS821D –MARCH 2013–REVISED DECEMBER 2013
www.ti.com
Table 5-1. L3 Master/Slave Connectivity
MASTERS
SLAVES
SD2
ARM M1 (128-bit)
ARM M2 (64-bit)
HDVICP2 VDMA
HDVPSS Mstr0
HDVPSS Mstr1
EMAC SW
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
USB2.0 DMA
USB2.0 Queue Mgr
PCIe Gen2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Media Controller
DeBug Access Port (DAP)
EDMA TPTC0 RD
EDMA TPTC0 WR
EDMA TPTC1 RD
EDMA TPTC1 WR
EDMA TPTC2 RD
EDMA TPTC2 WR
EDMA TPTC3 RD
EDMA TPTC3 WR
ISS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
120
System Interconnect
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