CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= 2.3 V, I = –18 mA
MIN
TYP
MAX
UNIT
V
V
Input voltage
All inputs
V
V
V
V
V
V
V
V
–1.2
V
IK
DDQ
DDQ
DDQ
DDQ
DDQ
I
= min to max, I = –1 mA
V
DDQ
– 0.1
1.7
OH
High-level output voltage
V
OH
= 2.3 V,
I
= –12 mA
OH
= min to max, I = 1 mA
0.1
0.6
0.4
OL
Low-level output
voltage
SDATA
= 2.3 V,
= 3.0 V,
I
I
= 12 mA
= 3 mA
= 1 V
V
OL
V
OL
DDI
OL
I
I
High-level output current
Low-level output current
Output voltage swing
= 2.3 V,
= 2.3 V,
V
V
–18
26
–32
35
mA
mA
V
OH
DDQ
DDQ
O
= 1.2 V
OL
O
V
O
For load condition see Figure 3
1.1
V
DDQ
– 0.4
Output differential cross
voltage
V
OX
V /2 − 0.2
DDQ
V /2
DDQ
V /2 + 0.2
DDQ
V
SDATA,
SCLK
V
DDQ
V
DDQ
V
DDQ
= 3.6 V,
= 2.7 V,
= 2.7 V,
V = 0 V to 3.6 V
+10/−50
10
μA
μA
μA
I
I
I
I
Input current
I
CLK, FBIN
V = 0 V to 2.7 V
I
High-impedance-state output
current
V
O
= V or GND
DDQ
10
OZ
Power-down current on V
DDQ
CLK at 0 MHz; Σ of I and AI
150
3
250
20
μA
μA
DD
DD
+ AV
DD
DDPD
Power down current on V
CLK at 0 MHz; V
= 3.6 V
DDI
DDQ
V
DDQ
= 2.7 V,
f
O
= 100 MHz
I
Dynamic current on V
All differential output pairs are terminated
with 120 Ω / C = 4 pF
205
230
mA
DD
DDQ
L
AI
Supply current on AV
AV = 2.7 V,
f = 100 MHz
O
4
1
6
2
mA
mA
(DD)
DD
DD
SCLK and
SDATA = 3.6 V
I
Supply current on V
V
DDI
= 3.6 V
DDI
DDI
C
C
Input capacitance
Output capacitance
V
V
= 2.5 V
= 2.5 V
V = V or GND
DDQ
2
2.5
3
3
pF
pF
I
DDQ
I
V
O
= V or GND
DDQ
2.5
3.5
O
DDQ
†
‡
All typical values are at respective nominal V
.
DDQ
The value of V is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input
OC
signal voltage and VCP is the complementary input signal voltage (see Figure 3).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
