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CDCV850IDGGR 参数 Datasheet PDF下载

CDCV850IDGGR图片预览
型号: CDCV850IDGGR
PDF下载: 下载PDF文件 查看货源
内容描述: [2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 20 页 / 809 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CDCV850  
2.5-V PHASE LOCK LOOP CLOCK DRIVER  
WITH 2-LINE SERIAL INTERFACE  
SCAS647D OCTOBER 2000 REVISED APRIL 2013  
switching characteristics over recommended ranges of operating free-air temperature (unless  
otherwisw noted)  
PARAMETER  
TEST CONDITIONS  
Test mode/CLK to any output  
SCLK to SDATA (acknowledge)  
Test mode/SDATA to Y-output  
Test mode/SDATA to Y-output  
100/133 MHz  
MIN  
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
Propagation delay time  
4
pd  
{
High-to low-level propagation delay time  
Output enable time  
500  
ns  
PHL  
en  
85  
35  
ns  
Output disable time  
ns  
dis  
Jitter (period), See Figure 6  
Jitter (cycle-to-cycle), See Figure 3  
Half-period jitter, See Figure 7  
30  
30  
30  
30  
ps  
jit(per)  
jit(cc)  
jit(hper)  
100/133 MHz  
ps  
100/133 MHz  
75  
75  
ps  
}
100 MHz/VID on CLK = 0.71 V  
120  
50  
120  
160  
70  
w
100 MHz/VID on CLK = 0.59 V  
0°C to 85°C  
ps  
ps  
W
100 MHz/VID on CLK = 0.82 V  
170  
50  
W
133 MHz/VID on CLK = 0.71 V  
180  
80  
t
(
Static phase offset, See Figure 4a  
)
}
100 MHz/VID on CLK = 0.71 V  
160  
90  
w
100 MHz/VID on CLK = 0.59 V  
120  
30  
40°C to 85°C  
W
100 MHz/VID on CLK = 0.82 V  
210  
80  
W
133 MHz/VID on CLK = 0.71 V  
150  
190  
140  
160  
130  
}
100 MHz/VID on CLK = 0.71 V  
190  
140  
160  
130  
ps  
ps  
ps  
ps  
Dynamic phase offset, SSC on, See Figure 4b and  
Figure 9  
}
133 MHz/VID on CLK = 0.71 V  
#
td  
(
)
}
100 MHz/VID on CLK = 0.71 V  
Dynamic phase offset, SSC off, See Figure 4b  
}
133 MHz/VID on CLK = 0.71 V  
Output clock slew rate, terminated with  
120Ω/14 pF, See Figures 1 and 8  
t
1
1
2
3
V/ns  
V/ns  
slr(o)  
Output clock slew rate, terminated with 120Ω/4 pF,  
See Figures 1 and 8  
t
t
slr(o)  
⏐⏐  
Output skew, See Figure 5  
75  
33.3  
ps  
kHz  
%
sk(o)  
SSC modulation frequency  
30  
SSC clock input frequency deviation  
0.00  
0.50  
§
#
||  
This time is for a PLL frequency of 100 MHz.  
According CK00 spec: 6 x I at 50 Ω and R = 475 Ω  
ref  
ref  
According CK00 spec: 5 x I at 50 Ω and R = 475 Ω  
ref  
ref  
According CK00 spec: 7 x I at 50 Ω and R = 475 Ω  
ref  
ref  
The parameter is assured by design but cannot be 100% production tested.  
All differential output pins are terminated with 120 Ω/4 pF  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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