欢迎访问ic37.com |
会员登录 免费注册
发布采购

CDCV850IDGGR 参数 Datasheet PDF下载

CDCV850IDGGR图片预览
型号: CDCV850IDGGR
PDF下载: 下载PDF文件 查看货源
内容描述: [2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 20 页 / 809 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号CDCV850IDGGR的Datasheet PDF文件第1页浏览型号CDCV850IDGGR的Datasheet PDF文件第2页浏览型号CDCV850IDGGR的Datasheet PDF文件第3页浏览型号CDCV850IDGGR的Datasheet PDF文件第5页浏览型号CDCV850IDGGR的Datasheet PDF文件第6页浏览型号CDCV850IDGGR的Datasheet PDF文件第7页浏览型号CDCV850IDGGR的Datasheet PDF文件第8页浏览型号CDCV850IDGGR的Datasheet PDF文件第9页  
CDCV850  
2.5-V PHASE LOCK LOOP CLOCK DRIVER  
WITH 2-LINE SERIAL INTERFACE  
SCAS647D OCTOBER 2000 REVISED APRIL 2013  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†  
Supply voltage range: V  
V
, AV  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V  
DDQ  
DD  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V  
DDI  
Input voltage range: V (except SCLK and SDATA) (see Notes 1 and 2) . . . . . . . . . 0.5 V to V  
+ 0.5 V  
+ 0.5 V  
+ 0.5 V  
+ 0.5 V  
I
DDQ  
V (SCLK, SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
I
DDI  
DDQ  
DDQ  
Output voltage range: V (except SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . 0.5 V to V  
O
V (SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
IK  
I
I
DDQ  
Output clamp current, I (V < 0 or V > V )  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
DDQ  
OK  
O
O
DDQ  
O
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W  
JA  
Storage temperature range T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. This value is limited to 3.6 V maximum.  
3. The package thermal impedance is calculated in accordance with JESD 51.  
recommended operating conditions (see Note 4)  
MIN  
2.3  
TYP  
MAX  
UNIT  
V
V
, AV  
2.7  
3.6  
DDQ  
DD  
Supply voltage  
V
(see Note 5)  
2.3  
DDI  
CLK, CLK, HCSL Buffer only  
CLK, CLK  
0
0.24  
0.4  
0.3  
V
DDQ  
Low level input voltage, V  
V
V
IL  
FBIN, FBIN  
V
/2 0.18  
DDQ  
SDATA, SCLK  
0.3 × V  
DDI  
CLK, CLK, HCSL Buffer only  
CLK, CLK  
0.66  
0.4  
0.71  
V
DDQ  
+ 0.3  
High level input voltage, V  
IH  
FBIN, FBIN  
V
/2 + 0.18  
DDQ  
SDATA, SCLK  
0.7 × V  
–0.3  
0.36  
0.2  
DDI  
DC input signal voltage (see Note 6)  
Differential input signal voltage, V (see Note 7)  
V
DDQ  
V
DDQ  
V
DDQ  
+ 0.3  
+ 0.6  
+ 0.6  
V
V
DC  
AC  
CLK, FBIN  
CLK, FBIN  
ID  
Input differential pair cross-voltage, V (see Note 8)  
0.45×(V V )  
0.55×(V V )  
V
mA  
V
IX  
IH  
IL  
IH  
IL  
High-level output current, I  
12  
OH  
12  
3
Low-level output current, I  
OL  
SDATA  
mA  
V/ns  
kHz  
kHz  
°C  
Input slew rate, SR (see Figure 8)  
SSC modulation frequency  
1
4
30  
33.3  
SSC clock input frequency deviation  
0
0.50  
Operating free-air temperature, T  
40  
85  
A
NOTES: 4. Unused inputs must be held high or low to prevent them from floating.  
5. All devices on the serial interface bus, with input levels related to V , must have one common supply line to which the pullup resistor  
DDI  
is connected to.  
6. DC input signal voltage specifies the allowable dc execution of differential input.  
7. Differential input signal voltage specifies the differential voltage |VTR VCP| required for switching, where VTR is the true input level  
and VCP is the complementary input level.  
8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be  
crossing.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
 复制成功!