CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
60
MAX
140
60%
10
UNIT
f
Clock frequency
MHz
(CLK)
Input clock duty cycle
40%
†
Stabilization time
μs
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
timing requirements for the 2-line serial interface over recommended ranges of operating
free-air temperature and VDDI from 3.3 V to 3.6 V (see Figure 10)
MIN
MAX
UNIT
kHz
μs
f
t
t
t
t
SCLK frequency
Bus free time
100
(SCLK)
4.7
4.7
4.0
4.7
4.0
(BUS)
†
START setup time
μs
su(START)
†
START hold time
μs
h(START)
w(SCLL)
w(SCLH)
SCLK low pulse duration
μs
t
t
t
t
t
t
SLCK high pulse duration
SDATA input rise time
SDATA input fall time
SDATA setup time
μs
ns
ns
ns
ns
μs
1000
300
r(SDATA)
f(SDATA)
su(SDATA)
h(SDATA)
su(STOP)
250
0
SDATA hold time
STOP setup time
4
†
This conforms to I2C specification, version 2.1.
6
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TI [ TEXAS INSTRUMENTS ]
