CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D
−
OCTOBER 2000
−
REVISED APRIL 2013
D
Phase-Lock Loop Clock Driver for Double
D
D
D
D
D
D
D
D
D
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 140 MHz
Low Jitter (cyc−cyc):
±75
ps
Distributes One Differential Clock Input to
Ten Differential Outputs
Two-Line Serial Interface Provides Output
Enable and Functional Control
Outputs Are Put Into a High-Impedance
State When the Input Differential Clocks
Are <20 MHz
48-Pin TSSOP Package
Consumes <250-μA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
DGG PACKAGE
(TOP VIEW)
description
The CDCV850 is a high-performance, low-skew,
21
28
low-jitter zero delay buffer that distributes a
22
27
differential clock input pair (CLK, CLK) to ten
23
26
differential pairs of clock outputs (Y[0:9], Y[0:9])
24
25
and one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are con-
trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,
SCLK), and the analog power input (AV
DD
). A two-line serial interface can put the individual output clock pairs
in a high-impedance state. When the AV
DD
terminal is tied to GND, the PLL is turned off and bypassed for test
purposes.
The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line
serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).
Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to
enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit
is written to the control register. The registers must be accessed in sequential order (i.e., random access of the
registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in
applications where this programming option is not required (after power up, all output pairs will then be enabled).
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),
the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low
power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as changes to various 2-line serial registers that
affect the PLL. The CDCV850 is characterized in a temperature range from
−
40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
GND
Y0
Y0
V
DDQ
Y1
Y1
GND
GND
Y2
Y2
V
DDQ
SCLK
CLK
CLK
V
DDI
AV
DD
AGND
GND
Y3
Y3
V
DDQ
Y4
Y4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
Y5
Y5
V
DDQ
Y6
Y6
GND
GND
Y7
Y7
V
DDQ
SDATA
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y8
Y8
V
DDQ
Y9
Y9
GND
Copyright
©
2002, Texas Instruments Incorporated
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•
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1
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