CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
2-line serial interface
2-line serial interface slave address
A7
A6
A5
A4
A3
A2
A1
R/W
1
1
0
1
0
0
1
0
Writing to the device is accomplished by sequentially sending the device address D2 , the dummy bytes
H
(command code and the number of bytes), and the data bytes. This sequence is illustrated in the following
tables:
1 bit
7 bits
1 bit
R/W
1 bit
Ack
8 bits
1 bit
Ack
8 bits
Start Bit
Slave Address
Command Code
Byte Count = N
Ack
Data Byte 0
8 bits
Ack
1 bit
Data Byte 1
8 bits
Ack
Data Byte N
8 bits
Ack
1 bit
Stop
1 bit
1 bit
1 bit
2-line serial interface configuration command bitmap
The 2-line serial command bytes are used to control the output clock pairs (Y[0:9], Y[0:9]). The output clock pairs
are enabled after power up. During normal operation, the clock pairs can be disabled (set Hi-Z) or enabled
(running) by writing the corresponding bit to the data bytes in the following tables:
Byte 0: Enable/Disable Register
(H = Enable, L = Disable)
Byte 1: Enable/Disable Register
(H = Enable, L = Disable)
BIT
PINS
INITIAL
VALUE
DESCRIPTION
BIT
PINS
INITIAL
VALUE
DESCRIPTION
7
6
5
4
3
2
1
0
3, 2
H
H
H
H
H
H
H
H
Y0, Y0
Y1, Y1
Y2, Y2
Y3, Y3
Y4, Y4
Y5, Y5
Y6, Y6
Y7, Y7
7
6
5
4
3
2
1
0
29, 30
H
H
L
L
L
L
L
L
Y8, Y8
5, 6
27, 26
Y9, Y9
10, 9
−
−
−
−
−
−
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
20, 19
22, 23
46, 47
44, 43
39, 40
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
