CC1110Fx / CC1111Fx
data packets may be sent/received at a few
micro seconds interval. For isochronous
endpoints, an incoming packet will be lost if
there is no buffer available and a zero length
data packet will be sent if there is no data
packet ready for transmission when the USB
host requests data. Double buffering is not as
critical for bulk and interrupt endpoints as it is
for isochronous endpoint since packets will not
be lost. Double buffering, however, may
improve the effective data rate for bulk
endpoints.
USBCSOL.OUTPKT_RDY bit will be asserted
immediately and an interrupt will be generated
(if enabled) to signal that a new data packet
has
been
received.
The
USBCSOL.FIFO_FULL bit will be set when
there are two data packets in the OUT FIFO.
The AutoClear feature is supported for OUT
endpoints.
USBCSOL.OUTPKT_RDY
When
enabled,
bit is
the
cleared
automatically when USBMAXObytes have been
read from the OUT FIFO. The AutoClear
feature
USBCSOH.AUTOCLEAR=1.
is
enabled
by
The
setting
AutoClear
To enable double buffering for an IN endpoint,
USBCSIH.IN_DBL_BUF must be set to 1. To
enable double buffering for an OUT endpoint,
set USBCSOH.OUT_DBL_BUFto 1.
feature can be used to reduce the time the
data packet occupies the OUT FIFO buffer and
is typically used for bulk endpoints.
A complementary AutoSet feature is supported
for IN endpoints. When enabled, the
USBCSIL.INPKT_RDY bit is set automatically
when USBMAXIbytes have been written to the
IN FIFO. The AutoSet feature is enabled by
setting USBCSIH.AUTOSET=1. The AutoSet
feature can reduce the overall time it takes to
send a data packet and is typically used for
bulk endpoints.
12.16.6.3 FIFO Access
The endpoint FIFOs are accessed by reading
and writing to the registers in Table 36 on
Page 53. Writing to a register causes the byte
written to be inserted into the IN FIFO.
Reading a register causes the next byte in the
OUT FIFO to be extracted and the value of this
byte to be returned.
When a data packet has been written to an IN
FIFO, the USBCSIL.INPKT_RDY bit must be
set to 1. If double buffering is enabled, the
USBCSIL.INPKT_RDY bit will be cleared
immediately after it has been written and
another data packet can be loaded. This will
not generate an IN endpoint interrupt, since an
interrupt is only generated when a packet has
been sent. When double buffering is used
firmware should check the status of the
USBCSIL.PKT_PRESENT bit before writing to
the IN FIFO. If this bit is 0, two data packets
can be written. Double buffered isochronous
endpoints should only need to load two
packets the first time the IN FIFO is loaded.
After that, one packet is loaded for every USB
frame. To send a zero length data packet,
USBCSIL.INPKT_RDY should be set to 1
without loading a data packet into the IN FIFO.
12.16.6.4 Endpoint 1 - 5 Interrupts
The following events may generate an IN EPx
interrupt request (x indicates the endpoint
number):
A data packet that was loaded into the
IN FIFO has been sent to the USB host
(USBCSIL.INPKT_RDYshould be set to
1 when a new packet is ready to be
transferred. This bit will be cleared by
HW when the data packet has been
sent)
A
STALL
has
been
sent
Only
(USBCSIL.SENT_STALL=1).
Bulk/Interrupt endpoints can be stalled
The IN FIFO is flushed due to the
USBCSIH.FLUSH_PACKET bit being set
to 1
A data packet can be read from the OUT FIFO
when the USBCSOL.OUTPKT_RDY bit is 1. An
interrupt will be generated when this occurs, if
enabled. The size of the data packet is kept in
the USBCNTH:USBCNTL registers. Note that
Any
of
these
events
will
cause
USBIIF.INEPxIF to be asserted regardless
of the status of the IN EPx interrupt mask bit
USBIIE.INEPxIE. If the IN EPx interrupt
mask bit is set to 1, the CPU interrupt flag
IRCON2.USBIF will also be asserted. An
interrupt request is only generated if
IEN2.USBIE and USBIIE.INEPxIE are both
set to 1. The x in the register names refer to
the endpoint number 1 - 5)
this
value
is
only
valid
when
USBCSOL.OUTPKT_RDY=1. When the data
packet has been read from the OUT FIFO, the
USBCSOL.OUTPKT_RDYbit must be cleared. If
double buffering is enabled there may be two
data packets in the FIFO. If another data
packet
is
ready
when
the
USBCSOL.OUTPKT_RDY bit is cleared the
SWRS033H
Page 175 of 246
TI [ TEXAS INSTRUMENTS ]
