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CC1110F32RHHR 参数 Datasheet PDF下载

CC1110F32RHHR图片预览
型号: CC1110F32RHHR
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器,低于1GHz的射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 249 页 / 3133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CC1110Fx / CC1111Fx  
Endpoint 0 is controlled through the USBCS0  
register by setting the USBINDEXregister to 0.  
The USBCNT0 register contains the number of  
bytes received.  
The USB host tries to send a packet that  
exceeds the maximum packet size  
during the OUT Data stage  
The size of the DATA1 packet received  
during the Status stage is not 0  
12.16.5 Endpoint 0 Interrupts  
The firmware can also terminate the current  
transaction  
by  
setting  
the  
The following events may generate an EP0  
interrupt request:  
USBCS0.SEND_STALL bit to 1. The USB  
controller will then send a STALL handshake in  
response to the next requests from the USB  
host.  
A
data packet has been received  
(USBCS0.OUTPKT_RDY=1)  
A data packet that was loaded into the  
EP0 FIFO has been sent to the USB  
host (USBCS0.INPKT_RDY should be  
set to 1 when a new packet is ready to  
be transferred. This bit will be cleared by  
HW when the data packet has been  
sent)  
If an EP0 interrupt is caused by the assertion  
of the USBCS0.SENT_STALL bit, this bit  
should be de-asserted and firmware should  
consider the transfer as aborted (free memory  
buffers etc.).  
If EP0 receives an unexpected token during  
the Data stage, the USBCS0.SETUP_END bit  
will be asserted and an EP0 interrupt will be  
generated (if enabled properly). EP0 will then  
switch to the IDLE state. Firmware should then  
set the USBCS0.CLR_SETUP_ENDbit to 1 and  
An IN transaction has been completed  
(the interrupt is generated during the  
Status stage of the transaction)  
A
STALL  
has  
been  
sent  
abort  
the  
current  
transfer.  
If  
(USBCS0.SENT_STALL=1)  
USBCS0.OUTPKT_RDY is asserted, this  
indicates that another Setup Packet has been  
received that firmware should process.  
A control transfer ends due to a  
premature end of control transfer  
(USBCS0.SETUP_END=1)  
Any of these events will cause the  
USBIIF.EP0IF to be asserted regardless of  
the status of the EP0 interrupt mask bit  
USBIIE.EP0IE. If the EP0 interrupt mask bit  
is set to 1, the CPU interrupt flag  
IRCON2.USBIF will also be asserted. An  
interrupt request is only generated if  
IEN2.USBIE and USBIIE.EP0IE are both  
set to 1.  
12.16.5.2 SETUP Transactions (IDLE State)  
The control transfer consists of 2 - 3 stages of  
transactions (Setup - Data - Status or Setup -  
Status). The first transaction is a Setup  
transaction. A successful Setup transaction  
comprises three sequential packets (a token  
packet, a data packet, and a handshake  
packet), where the data field (payload) of the  
data packet is exactly 8 bytes long and are  
referred to as the Setup Packet. In the Setup  
stage of a control transfer, EP0 will be in the  
IDLE state. The USB controller will reject the  
data packet if the Setup Packet is not 8 bytes.  
Also, the USB controller will examine the  
contents of the Setup Packet to determine  
whether or not there is a Data stage in the  
control transfer. If there is a Data stage, EP0  
will switch state to TX (IN transaction) or RX  
12.16.5.1 Error Conditions  
When a protocol error occurs, the USB  
controller sends a STALL handshake. The  
USBCS0.SENT_STALL bit is asserted and an  
interrupt request is generated if the endpoint 0  
interrupt is properly enabled. A protocol error  
can be any of the following:  
(OUT  
transaction)  
when  
the  
An OUT token is received after  
USBCS0.DATA_END has been set to  
complete the OUT Data stage (the host  
tries to send more data than expected)  
USBCS0.CLR_OUTPKT_RDY bit is set to 1 (if  
USBCS0.DATA_END=0).  
When  
a
packet  
is  
received,  
the  
USBCS0.OUTPKT_RDYbit will be asserted and  
an interrupt request is generated (EP0  
interrupt) if the interrupt has been enabled.  
Firmware should perform the following when a  
Setup Packet has been received:  
An IN token is received after  
USBCS0.DATA_END has been set to  
complete the IN Data stage (the host  
tries to receive more data than  
expected)  
SWRS033H  
Page 172 of 246  
 
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