CC1110Fx / CC1111Fx
0xDE00: USBADDR - Function Address
Bit Field Name
UPDATE
Reset
R/W
Description
7
0
R
This bit is set when the USBADDRregister is written and cleared when the
address becomes effective.
6:0 USBADDR[6:0]
0000000 R/W
Device address
0xDE01: USBPOW - Power/Control Register
Bit
Field Name
Reset
R/W
Description
7
ISO_WAIT_SOF
0
R/W
When this bit is set to 1, the USB controller will send zero length data packets
from the time INPKT_RDYis asserted and until the first SOF token has been
received. This only applies to isochronous endpoints.
6:4
3
-
R0
R
Not used
RST
0
0
During reset signaling, this bit is set to1
2
RESUME
R/W
Drive resume signaling for remote wakeup. According to the USB Specification
the duration of driving resume must be at least 1 ms and no more than 15 ms.
It is recommended to keep this bit set for approximately 10 ms.
1
0
SUSPEND
0
0
R
Suspend mode entered. This bit will only be used when SUSPEND_EN=1.
Reading the USBCIFregister or asserting RESUMEwill clear this bit.
SUSPEND_EN
R/W
Suspend Enable. When this bit is set to 1, suspend mode will be entered when
USB bus has been idle for 3 ms.
0xDE02: USBIIF - IN Endpoints and EP0 Interrupt Flags
Bit
Field Name
Reset
R/W
Description
7:6
5
00
0
R0
Reserved
INEP5IF
INEP4IF
INEP3IF
INEP2IF
INEP1IF
EP0IF
R
H0
Interrupt flag for IN endpoint 5. Cleared by HW when read
4
3
2
1
0
0
0
0
0
0
R
H0
Interrupt flag for IN endpoint 4. Cleared by HW when read
Interrupt flag for IN endpoint 3. Cleared by HW when read
Interrupt flag for IN endpoint 2. Cleared by HW when read
Interrupt flag for IN endpoint 1. Cleared by HW when read
Interrupt flag for endpoint 0. Cleared by HW when read
R
H0
R
H0
R
H0
R
H0
0xDE04: USBOIF - Out Endpoints Interrupt Flags
Bit
Field Name
Reset
R/W
Description
7:6
5
00
0
R0
Reserved
OUTEP5IF
OUTEP4IF
OUTEP3IF
OUTEP2IF
OUTEP1IF
R
H0
Interrupt flag for OUT endpoint 5. Cleared by HW when read
4
3
2
1
0
0
0
0
0
-
R
H0
Interrupt flag for OUT endpoint 4. Cleared by HW when read
Interrupt flag for OUT endpoint 3. Cleared by HW when read
Interrupt flag for OUT endpoint 2. Cleared by HW when read
Interrupt flag for OUT endpoint 1. Cleared by HW when read
Not used
R
H0
R
H0
R
H0
R0
SWRS033H
Page 179 of 246
TI [ TEXAS INSTRUMENTS ]
