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CC1110F32RHHR 参数 Datasheet PDF下载

CC1110F32RHHR图片预览
型号: CC1110F32RHHR
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器,低于1GHz的射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 249 页 / 3133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CC1110Fx / CC1111Fx  
An isochronous data packet in the OUT FIFO  
may have bit errors. The hardware will detect  
this condition and set USBCSOL.DATA_ERROR.  
Firmware should therefore always check this  
bit when unloading a data packet.  
The word size can be byte (8 bits) or word (16  
bits). When word size transfer is used the  
ENDIAN register must be set correctly (see  
Section 12.5.7). The ENDIAN.USBRLE bit  
selects whether a word is read as little or big  
endian from the OUT FIFOs and the  
ENDIAN.USBWLEbit selects whether a word is  
written as little or big endian to the IN FIFOs.  
Writing and reading words for the different  
settings is shown in  
The AutoClear feature will typically not be used  
for isochronous endpoints since the packet  
size will increase or decrease from frame to  
frame.  
Figure 45 and Figure 46 respectively. Notice  
that the setting for these bits will be used for all  
endpoints. Consequently, it is not possible to  
have multiple DMA channels active at once  
that use different endianness. The ENDIAN  
register must be configured to use big endian  
for both read and write for a word size transfer  
to produce the same result as a byte size  
transfer of an even number of bytes. Word size  
transfers are slightly more efficient than byte  
transfers.  
12.16.7 DMA  
DMA should be used to fill the IN endpoint  
FIFOs and empty the OUT endpoint FIFOs.  
Using DMA will improve the read/write  
performance significantly compared to using  
the 8051 CPU. It is therefore highly  
recommended to use DMA unless timing is not  
critical or only a few bytes are to be  
transferred.  
There are no DMA triggers for the USB  
controller, meaning that DMA transfers must  
be triggered by firmware.  
Refer to Section 12.5 for more details  
regarding DMA.  
MSB LSB  
ENDIAN.USBWLE = 0  
SYNC  
PID  
MSB LSB MSB LSB  
MSB LSB CRC16 EOP  
To Host  
MSB LSB  
ENDIAN.USBWLE = 1  
SYNC  
PID  
LSB MSB LSB MSB  
LSB MSB CRC16 EOP  
To Host  
Figure 45: Writing Big/Little Endian  
SYNC  
PID  
B0  
B1  
B2  
B3  
Bn-1 Bn  
CRC16 EOP  
From Host  
ENDIAN.USBRLE = 0  
ENDIAN.USBRLE = 1  
B0  
B1  
B1  
B0  
Figure 46: Reading Big/Little Endian  
SWRS033H  
Page 177 of 246  
 
 
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