CC1110Fx / CC1111Fx
I2SCFG0.ULAWC must be 0 before writing a
byte of compressed data to the I2SDATH
register. The expansion takes one clock cycle
to perform, and then the result can be read
from the I2SDATH:I2SDATL registers.
Only one of the flags I2SCFG0.ULAWC and
I2SCFG0.ULAWE should be set to 1 when the
I2SCFG0.ENABbit is 0.
12.15.13 I2S Registers
To perform a compression I2SCFG0.ULAWE
must be 0 and I2SCFG0.ULAWCmust be 1. To
start the compression, an un-compressed 16-
bit sample should be written to the
This section describes all the registers used for
I2S control and status. The I2S registers reside
in XDATA memory space in the region 0xDF40
- 0xDF48. Table 33 on Page 52 gives an
overview of register addresses while the tables
in this section describe each register. Notice
that the reset values for the registers reflect a
configuration with 16-bit stereo samples and
44.1 kHz sample rate. The I2S is not enabled at
reset.
I2SDATH:I2SDATL
registers.
The
compression takes one clock cycle to perform,
and then the result can be read from the
I2SDATH register.
SWRS033H
Page 166 of 246
TI [ TEXAS INSTRUMENTS ]
