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CC1110F32RHHR 参数 Datasheet PDF下载

CC1110F32RHHR图片预览
型号: CC1110F32RHHR
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的SoC (系统级芯片)与MCU,存储器,低于1GHz的射频收发器和USB控制器 [Low-Power SoC (System-on-Chip) with MCU, Memory, Sub-1 GHz RF Transceiver, and USB Controller]
分类和应用: 存储射频控制器
文件页数/大小: 249 页 / 3133 K
品牌: TI [ TEXAS INSTRUMENTS ]
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CC1110Fx / CC1111Fx  
Notice that the DMA triggers I2SRX and  
ADC_CH6 share the same DMA trigger  
number (# 27) in the same way as I2STX and  
ADC_CH7 share DMA trigger number 28. This  
means that I2SRX can not be used together  
with ADC_CH6 and I2STX can not be used  
together with ADC_CH7. On the CC1111Fx ADC  
channels 6 and 7 cannot be used since P0_6  
and P0_7 I/O pins are not available.  
located in the I2SSTAT register. The interrupt  
enables and flags are summarized below.  
Interrupt enable bits:  
I2S RX: I2SCFG0.RXIEN  
I2S TX: I2SCFG0.TXIEN  
Interrupt flags:  
I2S RX: I2SSTAT.RXIRQ  
I2S TX: I2SSTAT.TXIRQ  
Refer to Table 51 on Page 107 for an overview  
of the DMA triggers.  
The TX interrupt flag I2SSTAT.TXIRQ is  
asserted together with IRCON2.I2STXIF  
when the internal TX buffer is empty and the  
I2S fetches the new data previously written to  
the I2SDATH:I2SDATL registers. The TX  
interrupt flag, I2SSTAT.TXIRQ, is cleared  
when I2SDATHregister is written. An interrupt  
12.15.4 Underflow/Overflow  
If the I2S attempts to read from the internal TX  
buffer when it is empty, an underflow condition  
occurs. The I2S will then continue to read from  
the  
data  
in  
the  
TX  
buffer,  
and  
I2SSTAT.TXUNFwill be asserted.  
request  
is  
only  
generated  
when  
If the I2S attempts to write to the internal RX  
buffer while it is full, an overflow condition  
occurs. The contents of the RX buffer will be  
overwritten and the I2SSTAT.RXOVF flag will  
be asserted.  
I2SCFG0.TXIEN and IEN2.I2STXIE are  
both set to 1.  
The RX interrupt flag I2SSTAT.RXIRQ is  
asserted together with TCON.I2SRXIF when  
the internal RX buffer is full and the contents of  
the RX buffer is copied to the pair of internal  
data registers that can be read from the  
Thus, when debugging an application,  
software may check for underflow/overflow  
when an interrupt is generated or when the  
application completes. The TXUNF / RXOVF  
flags should be cleared in software.  
I2SDATH:I2SDATL  
registers.  
The  
RX  
interrupt flag, I2SSTAT.RXIRQ, is cleared  
when the I2SDATH register is read. An  
interrupt request is only generated when  
I2SCFG0.RXIEN and IEN0.I2SRXIE are  
both set to 1.  
12.15.5 Writing a Word (TX)  
When each sample fits into a single byte or µ-  
Law compressed samples (always 8 bits) are  
written, i.e. µ-Law expansion is enabled  
(I2SCFG0.ULAWE=1), only the I2SDATH  
register needs to be written.  
Notice that interrupts will also be generated if  
the corresponding RXIRQ or TXIRQ flags are  
set from software, given that the interrupts are  
enabled.  
The I2S shares interrupt vector with USART 1,  
and the ISR must take this into account if both  
modules are used. Refer to 10.5 on Page 60  
for more details about interrupts.  
When each sample is more than 8 bits the low  
byte must be written to the I2SDATL register  
before the high byte is written to the I2SDATH  
register, hence writing the I2SDATH register  
indicates the completion of the write operation.  
12.15.3 I2S DMA Triggers  
When the I2S is configured to send stereo, i.e.  
I2SCFG0.TXMONO is 0, the I2SSTAT.TXLR  
flag can be used to determine whether the left-  
or right-channel sample is to be written to the  
data registers.  
There are two DMA triggers associated with  
the I2S interface, I2SRXand I2STX. The DMA  
triggers are activated by RX complete and TX  
complete events, i.e. the same events that can  
generated the I2S interrupt requests. The DMA  
triggers are not masked by the interrupt enable  
bits, I2SCFG0.RXIEN and I2SCFG0.TXIEN,  
hence a DMA channel can be configured to  
use the I2S receive/transmit data registers,  
I2SDATH:I2SDATL, as source or destination  
address and let RX and TX complete trigger  
the DMA.  
12.15.6 Reading a Word (RX)  
If each sample fits into a single byte or if µ-Law  
compression is enabled (I2SCFG0.ULAWC=1),  
only the I2SDATH register needs to be read.  
When each sample is more than 8 bits the low  
byte must be read from the I2SDATL register  
before the high byte is being read from the  
SWRS033H  
Page 163 of 246  
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