bq4015/Y
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
5 ns
Input pulse levels
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (T = T
A
, V
≤ V
CC
≤ V
)
OPR CCmin
CCmax
-70
-85/-85N
-120/-120N
Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
tRC
Read cycle time
70
-
-
85
-
-
120
-
-
120
120
60
-
tAA
Address access time
70
70
35
-
85
85
45
-
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
tACE
tOE
Chip enable access time
-
-
-
Output enable to output valid
Chip enable to output in low Z
-
-
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
5
0
0
10
5
0
0
0
10
5
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
-
-
0
-
25
25
-
35
25
-
0
45
35
-
0
10
5