bq4015/Y
Power-Down/Power-Up Cycle (T = T
)
OPR
A
Symbol
tPF
Parameter
Minimum
Typical
Maximum
Unit
µs
Conditions
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
300
10
0
-
-
-
-
-
-
tFS
µs
tPU
VCC slew, VSO to VPFD (max.)
µs
Time during which
SRAM is write-protected
after VCC passes VPFD on
power-up.
tCER
Chip enable recovery time
40
10
40
80
-
120
-
ms
years
µs
Data-retention time in
absence of VCC
T
A = 25°C. (2)
tDR
Delay after VCC slews
down past VPFD before
SRAM is write-
tWPT
Write-protect time
100
150
protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
9
TI [ TEXAS INSTRUMENTS ]
