bq29330
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SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)
KACT = (VOUT(4-5)– V(OUTR)) / VREF = (VREF + (1 + K) × VOS) – (VREF + (1 + K) × VOS– K ×
VREF)/VREF = K × VREF/VREF = K
Step 5
Calculate the actual offset value where:
VOS(ACT) = (V(OUTR)– VREF) / (1 + KACT
)
Step 6
Calibrated cell voltage is calculated by:
VCn – VC(n+1) = { VREF + (1 + KACT ) × VOS(ACT)– V(CELLOUT)}/KACT = {VOUT(4-5)– V(CELLOUT)}/KACT
To seek greater accuracy, it is better to measure VOS(ACT) for each cell voltage.
Set CAL1=0, CAL0=0, CELL1=0, CELL0=1, VMEN=1.
Set CAL1=0, CAL0=0, CELL1=1, CELL0=0, VMEN=1.
Set CAL1=0, CAL0=0, CELL1=1, CELL0=1, VMEN=1.
Measure VOUT(3-4), VOUT(2-3), VOUT(1-2)
,
VC4 – VC5 = {VOUT(4-5)– V(CELLOUT)}/KACT
VC3 – VC4 = {VOUT(3-4)– V(CELLOUT)}/KACT
VC2 – VC3 = {VOUT(2-3)– V(CELLOUT)}/KACT
VC1 – VC2 = {VOUT(1-2)– V(CELLOUT)}/KACT
BATTERY PACK AND BATTERY STACK MEASUREMENTS
The PACK (battery pack) and VC1 (battery stack) inputs can be translated to the CELL+, CELL– outputs of the
bq29330 through control bits in the FUNCTION_CONTROL register. If PACK is set, then the input at the PACK
is divided by 18 and presented at the CELL+, CELL– outputs. If the BAT bit is set, then the input to VC1 is
divided by 18 and presented at the CELL+, CELL– outputs. If setting both bits at the same time, VC1 is
presented at the CELL+, CELL– outputs.
CELL BALANCE CONTROL
The cell balance control allows a small bypass path to be controlled for any one series element. The purpose of
this bypass path is to reduce the current into any one cell during charging to bring the series elements to the
same voltage. Series resistors placed between the input pins and the positive series element nodes control the
bypass current value. Individual series element selection is made using bits 4 through 7 of CELL_SEL register.
Series input resistors between 500 Ω and 1 kΩ are recommended for effective cell balancing.
XALERT (XALERT)
XALERT is driven Low, when WDF, OL, SCC, or SCD OC are detected. To clear XALERT, toggle (from 0, set to
1, then reset to 0) STATE_CONTROL, LTCLR (bit 7), then read the STATUS register.
THERMISTOR DRIVE CIRCUIT (TOUT)
The TOUT pin can be enabled to drive a thermistor from REG. The typical thermistor resistance is 10 kΩ at
25°C. The default state for this is OFF to conserve power. The maximum output impedance is 100 Ω. TOUT is
enabled in FUNCTION_CONTROL register (bit 3).
GENERAL PURPOSE OPEN DRAIN DRIVE CIRCUIT (GPOD)
The General Purpose Open Drain output has 1-mA current source drive with a maximum output voltage of 25 V.
The OD output is enabled or disabled by OUTPUT_CONTROL register (bit 4) and has a default state of OFF.
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