bq29330
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SLUS673A – SEPTEMBER 2005 – REVISED DECEMBER 2005
AC TIMING REQUIREMENTS (I
2
C compatible serial interface)
T
A
= 25°C, CREG = 1
µF,
VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
t
r
t
f
t
w(H)
t
w(L)
t
su(STA)
t
h(STA)
t
su(DAT)
t
h(DAT)
t
su(STOP)
t
su(BUF)
t
v
t
h(CH)
f
SCL
SCLK, SDATA rise time
SCLK, SDATA fall time
SCLK pulse width high
SCLK pulse width low
Setup time for start condition
Start condition hold time after which first clock pulse is generated
Data setup time
Data hold time
Setup time for Stop condition
Time the bus must be free before new transmission can start
Clock low to data out valid
Data out hold time after clock low
Clock frequency
t
su(STA)
SCLK
t
r
SDATA
Start
Condition
t
h(STA)
SCLK
SDATA
1
MSB
Start Condition
t
v
t
su(STOP)
SCLK
SDATA
1
MSB
2
3
7
8
9
ACK
Stop Condition
t
su(BUF)
2
t
f
Stop
Condition
t
h(ch)
t
w(H)
t
w(L)
t
f
t
r
MIN
MAX
1000
300
UNIT
ns
ns
µs
µs
µs
µs
ns
µs
µs
µs
4
4.7
4.7
4
250
0
4
4.7
900
10
0
400
ns
ns
kHz
SDA
Input
t
h(DAT)
SDA
Change
t
su(DAT)
3
7
8
9
ACK
10
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