bq29330
www.ti.com
SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
AC TIMING REQUIREMENTS (I2C compatible serial interface)
TA = 25°C, CREG = 1 µF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tr
SCLK, SDATA rise time
1000
300
ns
ns
µs
µs
µs
µs
ns
µs
µs
µs
ns
ns
kHz
tf
SCLK, SDATA fall time
tw(H)
SCLK pulse width high
4
4.7
4.7
4
tw(L)
SCLK pulse width low
tsu(STA)
th(STA)
tsu(DAT)
th(DAT)
tsu(STOP)
tsu(BUF)
tv
Setup time for start condition
Start condition hold time after which first clock pulse is generated
Data setup time
250
0
Data hold time
Setup time for Stop condition
Time the bus must be free before new transmission can start
Clock low to data out valid
4
4.7
900
400
th(CH)
fSCL
Data out hold time after clock low
Clock frequency
10
0
t
t
f
t
r
su(STA)
t
t
w(L)
w(H)
SCLK
t
r
t
f
SDATA
Start
Stop
Condition
SDA
Input
SDA
Change
Condition
t
h(ch)
t
t
h(DAT)
su(DAT)
t
h(STA)
1
2
3
7
8
9
SCLK
MSB
ACK
SDATA
Start Condition
t
v
t
su(STOP)
SCLK
1
2
3
7
8
9
t
su(BUF)
MSB
SDATA
ACK
Stop Condition
10
TI [ TEXAS INSTRUMENTS ]
