bq29330
www.ti.com
SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION
LOW DROP OUTPUT REGULATOR (LEDOUT)
The inputs for this regulator can be derived from the VCC or BAT terminals. The output is a fixed voltage of
typically 3.3 V with the minimum output capacitance for stable operation of 2.2 µF and is also internally current
limited. This output is used for LED drive, power supply source for REG (2.5 V) and bq29330 internal circuit.
During normal operation, the regulator limits output current to typically 50 mA. Until the internal regulator circuit is
correctly powered, the DSG and CHG FET drives are low (FETs = OFF).
LOW DROP OUTPUT REGULATOR (REG)
The inputs for this regulator can be derived from the LED (3.3 V). The output is typically 2.5 V with the minimum
output capacitance for stable operation of 1 µF and is also internally current limited. During normal operation, the
regulator limits output current to typically 50 mA.
INITIALIZATION
From a shutdown situation, the bq29330 requires a voltage greater that start-up voltage (VSTARTUP) applied to the
PACK pin to enable its integrated regulator and provide the regulators power source. Once the REG output is
stable, the power source of the regulator is switched to VCC.
After the regulator has started, it then continues to operate through the VCC input. If the VCC input is below the
minimum operating range, then the bq29330 will not operate if the supply to the PACK input is removed.
If the voltage at VLED falls below about 2.3 V, the internal circuit turns off the FETs and disables all controllable
functions including the REG, LEDOUT, and TOUT outputs.
The initial state of the CHG and DSG FET drive is low (OFF) and the ZVCHG FET drive is low (ON).
OVERLOAD DETECTION
The overload detection is used to detect abnormal currents in the discharge direction. This feature is used to
protect the pass FETs, cells, and any other inline components from excessive discharge current conditions. The
detection circuit also incorporates a blanking delay before driving the control for the pass FETs to the OFF state.
The overload sense voltage is set in the OLV register, and delay time is set in the OLD register. The thresholds
can be individually programmed from 50 mV to 205 mV in 5-mV steps with the default being 50 mV.
If the RSNS bit in the FUNCTION_CTL register is set to 1, then the voltage threshold, programmable step size,
and hysteresis is divided by 2.
SHORT CIRCUIT IN CHARGE AND SHORT CIRCUIT IN DISCHARGE DETECTION
The short current circuit in charge and short circuit in discharge detections are used to detect severe abnormal
current in the charge and discharge directions, respectively. This safety feature is used to protect the pass FETs,
cells, and any other inline components from excessive current conditions. The detection circuit also incorporates
a blanking delay before driving the control for the pass FETs to the OFF state. The short circuit in charge
threshold and delay time are set in the SCC register. The short circuit in discharge threshold and delay time are
set in the SCD register. The short-circuit thresholds can be programmed from 100 mV to 475 mV in 25-mV steps.
If the RSNS bit in the FUNCTION_CTL register is set to 1, then the voltage threshold, programmable step size,
and hysteresis is divided by 2.
OVERLOAD, SHORT CIRCUIT IN CHARGE AND SHORT CIRCUIT IN DISCHARGE DELAY
The overload delay (default = 1 ms) allows the system to momentarily accept a high current condition without
disconnecting the supply to the load. The delay time can be increased via the OLD register which can be
programmed for a range of 1 ms to 31 ms with 2-ms steps.
The short circuit in charge and short circuit in discharge delays (default = 0 µs) are programmable in the SCC
and SCD registers, respectively. These registers can be programmed from 0 µs to 915 µs with 61-µs steps.
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