bq29330
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SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)
LATCH CLEAR (LTCLR)
When a protection fault occurs, the state is latched. To clear the fault flag, toggle (from 0, set 1, then reset to 0)
the LTCLR bit in the STATE_CONTROL register (bit 7). The OL, SCC, SCD, and WDF bits are unlatched by this
function. The FETs can now be controlled by programming the OUTPUT_CONTROL register, and the XALERT
output can be cleared by reading the STATUS register.
STATUS Register
Fault Timeout
Read
Expired
FET Control Access
by Host
Fault Flag Set
LTCLR Bit
XALERT Output
Figure 1. LTCLR and XLAERT Clear Timing
POR and WATCHDOG RESET (XRST)
The XRST pin is activated by activation of the REG output. This holds the host in reset for the duration of the
tRST period, allowing the VREG to stabilize before the host is released from reset. When the regulator power is
down, XRST is active below the regulator’s voltage of 1.8 V. Also, when a watchdog fault is detected, the XRST
is also activated to ensure a valid reset of the battery management host.
V
REGTH+
REG Output
V
REGTH-
t
RST
RST Output
Figure 2. XRST Timing Chart – Power Up and Power Down
WATCHDOG INPUT (WDI)
The WDI input is required as a time base for delay timing when determining fault detection and is used as part of
the system watchdog.
Initially, the watchdog monitors the host oscillator start-up; if there is no response from the host within tWDINT of
tRST expiring, then the bq29330 turns CHG, DSG, and ZVCHG FETs off. It then activates the XRST output in an
attempt to reset the host.
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