bq29330
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SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
FUNCTIONAL DESCRIPTION (continued)
Once the watchdog has been started during this wake-up period, it monitors the host for an oscillation stop
condition which is defined as a period of tWDWT where no clock input is received. If an oscillator stop condition is
identified, then the watchdog turns the CHG, DSG, and ZVCHG FETs off. The bq29330 then activates the XRST
output in an attempt to reset the host.
If the host clock oscillation is started after the reset, the bq29330 still has the WDF flag set until it is cleared. See
the LTCLR section for further details on clearing the fault flags.
During Sleep mode, the watchdog function is not disabled.
WDRST = L
REG Output
t
WDTINT (500 ms)
RST Output
t
WDTINT (500 ms)
t
RST
WDI Input
XALERT
CHG, DSG, and
FET Control
ZVCHG = OFF
Access by Host
WDRST = H
REG Output
t
WDTINT (500 ms)
Twice
RST Output
t
WDTINT (500 ms)
t
t
RST
RST
t
RST
t
WDTINT (500 ms)
WDI Input
XALERT
FET Control
CHG, DSG, and
ZVCHG = OFF
Access by Host
Figure 3. Watchdog Timing Chart – WDI Fault at Start-up
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