bq29330
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SLUS673A–SEPTEMBER 2005–REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS (Continued)
FET DRIVE CIRCUIT, TA = 25°C, CREG = 1 µF, CL = 2.2 µF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO(FETOND) = V(DSG)– Vpack TA = 25°C
MIN
7.5
8
TYP MAX
UNIT
12
12
12
12
3.5
15.5
16
V
VGS connect 10 MΩ
TA = –40°C to 110°C
TA = 25°C
Output voltage, charge,
and discharge FETs on
VO(FETON)
VO(FETONC) = V(CHG)– VBAT
7.5
8
15.5
16
V
V
V
VGS connect 10 MΩ
TA = –40°C to 110°C
V(ZCHG)
ZVCHG clamp voltage
BAT = 4.5 V
3.3
3.7
0.2
0.2
VFETOND = VDSG –Vpack
VFETONC = VCHG –VBAT
VO(FETOF Output voltage, charge,
and discharge FETs off
F)
V(CHG)
V(DSG)
V(CHG)
V(DSG)
:
Vpack ≥ Vpack+4 V
400 1000
400 1000
tr
tf
Rise time
Fall time
CL = 4700 pF
CL = 4700 pF
µs
µs
:
VBAT ≥ VBAT+4 V
:
Vpack+VCHG (FETON) ≥ pack +1 V
VC1+ VDSG (FETON) ≥ VC1 +1 V
40
40
200
200
:
LOGIC, TA = 25°C, CREG = 1 µF, CL = 2.2 µF, VCC or BAT = 14 V (unless otherwise noted)
XALERT
60
6
100
10
3
200
20
R(PUP)
Internal pullup resistance SDATA, SCLK
TA = –40°C to 110°C
TA = –40°C to 110°C
kΩ
XRST
1
6
XALERT
0.2
0.4
0.6
0.4
SDATA, IOUT = 200 µA
Low Logic level output
voltage
GPOD, IOUT = 50 µA
VOL
V
VCC or BAT = 7 V,
VREG = 1.5 V,
XRST, IOUT = 200 µA
VIH
SCLK (hysteresis input)
Hysteresis
450
mV
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, CREG = 1 µF, CL = 2.2 µF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
250
50
TYP
MAX
UNIT
ms
µs
tWDTINT
tWDWT
tRST
WDT start up detect time
WDT detect time
500
100
250
1000
150
XRST Active high time
100
560
µs
9
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