bq24707
bq24707A
SLUSA78B –JULY 2010–REVISED MARCH 2011
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If input current rises above 108% of the input current limit set point, the charger shuts down immediately to let
the input current fall fast. After stopping charge, the charger soft restarts to charge the battery if the adapter still
has power left to charge the battery. This prevents overloading the adapter to crash when system has a high and
fast loading transient. The wait time between shut down and restart charging is a natural response time of the
input current limit loop.
Table 6. Input Current Register (0x3FH), Using 10mΩ Sense Resistor
BIT
0
BIT NAME
DESCRIPTION
–
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
Not used.
1
–
2
–
3
–
4
–
5
–
6
–
7
Input Current, DACIIN 0
0 = Adds 0mA of input current.
1 = Adds 128mA of input current.
8
Input Current, DACIIN 1
Input Current, DACIIN 2
Input Current, DACIIN 3
Input Current, DACIIN 4
Input Current, DACIIN 5
0 = Adds 0mA of input current.
1 = Adds 256mA of input current.
9
0 = Adds 0mA of input current.
1 = Adds 512mA of input current.
10
11
12
0 = Adds 0mA of input current.
1 = Adds 1024mA of input current.
0 = Adds 0mA of input current.
1 = Adds 2048mA of input current.
0 = Adds 0mA of input current.
1 = Adds 4096mA of input current.
13
14
15
–
–
–
Not used.
Not used.
Not used.
Adapter Detect and ACOK Output
The IC uses an ACOK comparator to determine the source of power on the VCC pin, either from the battery or
adapter. An external resistor voltage divider attenuates the adapter voltage before it goes to ACDET. The
adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage
but lower than the maximum allowed adapter voltage.
The open drain ACOK output requires an external pull-up resistor to the system digital rail for a high level. It can
be pulled to ground under the following conditions:
•
•
•
V
VCC > UVLO;
2.4V < VACDET (not in low input voltage condition);
VCC–VSRN > 245mV (not in sleep mode);
V
The default delay is 1.3s for bq24707 and 1.2ms for bq24707A after ACDET has valid voltage to make ACOK
pull low. It can be reduced by a SMBus command (ChargeOption() bit[15] = 0 ACOK delay 1.3s for bq24707 and
1.2ms for bq24707A, bit[15] = 1 ACOK no delay). To change this option, the VCC pin voltage must be above
UVLO and the ACDET pin voltage must be above 0.6V to enable IC SMBus communication and set
ChargeOption() bit[15] to 1 to disable the ACOK deglitch timer.
Enable and Disable Charging
In Charge mode, the following conditions have to be valid to start charge:
•
•
•
Charge is enabled via SMBus (ChargeOption() bit [0] = 0, default is 0, charge enabled);
ILIM pin voltage higher than 105mV;
All three regulation limit DACs have a valid value programmed;
18
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