bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A –NOVEMBER 2011–REVISED MARCH 2012
Data Output
by Transmitter
Not Acknowledge
Acknowledge
Data Output
by Receiver
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 30. Acknowledge on the I2C Bus
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgment
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
Sr
or
P
ACK
ACK
or
Sr
Clock Line Held Low While
Interrupts are Serviced
Figure 31. Bus Protocol
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
TI [ TEXAS INSTRUMENTS ]
