bq24160, bq24161
bq24163, bq24168
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SLUSAO0A –NOVEMBER 2011–REVISED MARCH 2012
Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature.
For the bq24160/3/8, the WARM and COOL thresholds are not independently programmable. The COOL and
WARM NTC resistances for a selected resistor divider are calculated using the following equations:
RLO ´ 0.564 ´ RHI
RCOOL =
RLO - RLO ´ 0.564 - RHI ´ 0.564
(3)
RLO ´ 0.383 ´ RHI
RWARM =
RLO - RLO ´ 0.383 - RHI ´0.383
(4)
VBAT(REG)
1 x Charge/
0.5 x Charge
VDRV
DISABLE -140 mV
TS COLD
+
TS COOL
TS WARM
+
+
VDRV
TS HOT
+
RHI
TS
PACK+
TEMP
bq2416x
RLO
PACK-
Figure 26. TS Circuit
Thermal Regulation and Protection
During the charging process, to prevent chip overheating, the bq2416x monitors the junction temperature, TJ, of
the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The
charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq2416x if the die temperature rises too high. At any state, if
TJ exceeds TSHTDWN, the bq2416x suspends charging and disables the buck converter. During thermal shutdown
mode, the buck converter is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT
and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new charging
cycle begins when TJ falls below TSHTDWN by approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq2416x enters the low-power sleep mode if the voltage on VSUPPLY falls below the sleep-mode entry
threshold, VBAT+VSLP, and VSUPPLY is higher than the undervoltage lockout threshold, VUVLO. This feature
prevents draining the battery during the absence of VSUPPLY. When VSUPPLY < VBAT+ VSLP, the bq2416x turns off
the PWM converter, turns the battery FET on and drives BGATE to GND, sends a single 128μs pulse on the
STAT and INT outputs and updates the STATx and FAULT_x bits in the status registers. Once VSUPPLY > VBAT
+
VSLP, the STATx and FAULT_x bits are cleared and the device initiates a new charge cycle.
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