bq24160, bq24161
bq24163, bq24168
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SLUSAO0A –NOVEMBER 2011–REVISED MARCH 2012
OTG_LOCK Bit (USB Lockout)
The OTG_LOCK bit is used to prevent any charging from USB input regardless of the SUPPLY_SEL
bit and IN supply status. For systems using OTG supplies, it is not desirable to charge from an OTG
source. Doing so would mean draining the battery by allowing it to effectively charge itself. Write a “1”
to OTG_LOCK to lock out the USB input. Write a “0” to OTG_LOCK to return to normal operation.
During OTG lock, the USB input is ignored and DRV does not come up. The watchdog timer must be
reset while in USB_LOCK to maintain the USB lockout state. This prevents the USB input from being
permanently locked out for cases where the host loses I2C communication with OTG_LOCK set (i.e.,
discharged battery from OTG operation). See the Safety Timer and Watchdog Timer section for more
details.
EN_NOBATOP (No Battery Operation with Termination Disabled)
The EN_NOBATOP bit is used to enable operation when termination is disabled and no battery is
connected. This is useful for cases where the PA is connected to the BAT pin and it desired to do a
GSM calibration in the factory. For this application, the TE bit (Bit 2 in Register 0x02h) should be set to
a “0” to disable termination and the EN_NOBATOP should be set to a “1”. This feature should not be
used during normal operation as it disables the BATOVP and the reverse boost protection circuits.
Control Register (READ/WRITE)
Memory location: 02, Reset state: 1000 1100
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
RESET
Write only
Write: 1 – Reset all registers to default values
0 – No effect
Read: always get “1”
B6
B5
B4
IUSB_LIMIT_2
IUSB_LIMIT_1
IUSB_LIMIT _0
Read/Write
Read/Write
Read/Write
000 – USB2.0 host with 100mA current limit
001 – USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB host/charger with 800mA current limit
100 – USB3.0 host with 900mA current limit
101 – USB host/charger with 1500mA current limit
110–111 – NA (default 000(1)
)
B3
EN_STAT
Read/Write
1 – Enable STAT output to show charge status,
0-Disable STAT output for charge status. Fault interrupts are still show even when
EN_STAT = 0. (default 1)
B2
B1
TE
CE
Read/Write
Read/Write
Read/Write
1 – Enable charge current termination,
0-Disable charge current termination (default 1)
1 – Charging is disabled
0 – Charging enabled (default 0)
B0 (LSB)
HZ_MODE
1 – High impedance mode
0 – Not high impedance mode (default 0)
(1) When in DEFAULT mode, the D+/D– (bq24160) or PSEL (bq24161/8) inputs determine the input current limit for the USB input.
RESET Bit
The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write “1” to
RESET bit to reset all the registers to default values and place the bq2416x into DEFAULT mode and
turn off the watchdog timer. The RESET bit is automatically cleared to zero once the bq2416x enters
DEFAULT mode.
CE Bit (Charge Enable)
The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic
level (0) on this bit enables the charge and a high logic level (1) disables the charge. When charge is
disabled, the SYS output regulates to VSYS(REG) and battery is disconnected from the SYS.
Supplement mode is still available if the system load demands cannot be met by the supply.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
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