bq24160, bq24161
bq24163, bq24168
SLUSAO0A –NOVEMBER 2011–REVISED MARCH 2012
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HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance
mode. A low logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low
quiescent current state called high impedance mode. When in high impedance mode, the converter is
off and the battery FET and BGATE are on. The load on SYS is supplied by the battery.
Control/Battery Voltage Register (READ/WRITE)
Memory location: 03, Reset state: 0001 0100
BIT
B7 (MSB)
B6
NAME
VBREG5
VBREG4
VBREG3
VBREG2
VBREG1
VBREG0
IINLIMIT
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
Battery Regulation Voltage: 640 mV (default 0)
Battery Regulation Voltage: 320 mV (default 0)
Battery Regulation Voltage: 160 mV (default 0)
Battery Regulation Voltage: 80 mV (default 1)
Battery Regulation Voltage: 40 mV (default 0)
Battery Regulation Voltage: 20 mV (default 1)
B5
B4
B3
B2
B1
Input Limit for IN input-
0 – 1.5A
1 – 2.5A (default 0)
B0 (LSB)
D+/D–_EN
Read/Write
0 – Normal state, D+/D- Detection done
1 – Force D+/D– Detection. Returns to “0” after detection is done. (default 0)
•
Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
Vender/Part/Revision Register (READ only)
Memory location: 04, Reset state: 0100 0000
BIT
B7 (MSB)
B6
NAME
Vender2
Vender1
Vender0
PN1
Read/Write
Read only
Read only
Read only
Read only
Read only
FUNCTION
Vender Code: bit 2 (default 0)
Vender Code: bit 1 (default 1)
Vender Code: bit 0 (default 0)
For I2C Address 6Bh:
00: bq2416x
B5
B4
B3
PN0
01–11: Future product spins
B2
B1
Revision2
Revision1
Revision0
Read only
Read only
Read only
000: Revision 1.0
001: Revision 1.1
010: Revision 2.0
B0 (LSB)
011: Revision 2.1
100: Revision 2.2
101: Revision 2.3
110-111: Future Revisions
30
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