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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Frame Time
VBP = 0
VFP = 0
VSW = 1
LPP_B10 + LPP
(1 to 2048)
Line
Time
LCD_HSYNC
LCD_VSYNC
1, L
Data
1, L:
P, L
1, 1:
P, 1
1, 2:
P, 2
1, 3:
P, 3
1, 4:
P, 4
1, 5:
P, 5
1, 6:
P, 6
1, L
P, L
1, 1
P, 1
1, 2
P, 2
LCD_DATA[7:0]
1, L−1
P, L−1
1, L−4
P, L−4
1, L−3 1, L−2 1, L−1
P, L−1
P, L−3 P, L−2
LCD_AC_BIAS_EN
ACB
ACB
(0 to 255)
(0 to 255)
10
11
10
LCD_HSYNC
LCD_PCLK
1, 5 2, 5
P, 5
1, 6 2, 6
P, 6
LCD_DATA[7:0]
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 5
HFP
HSW
HBP
PPLMSB + PPLLSB
16 x (1 to 2048)
Line 6
(1 to 256)
(1 to 64)
(1 to 256)
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-83. LCD Raster-Mode Passive
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
205
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