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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
6
LCD_AC_BIAS_EN
8
LCD_VSYNC
LCD_HSYNC
10
10
11
1
3
2
LCD_PCLK
(passive mode)
4
5
LCD_D[7:0]
(passive mode)
1, 1 2, 1
P, 1
1, 2 2, 2
P, 2
1
3
2
LCD_PCLK
(active mode)
4
5
LCD_DATA[23:0]
(active mode)
1, 1 2, 1
P, 1
VBP = 0
VFP = 0
VWS = 1
PPLMSB + PPLLSB
16 x (1 to 2048)
PPLMSB + PPLLSB
16 x (1 to 2048)
HSW
HBP
HFP
(1 to 256)
(1 to 64)
(1 to 256)
Line 1
Line 1 for active
Line 2 for passive
A. The dashed portion of LCD_PCLK is only shown as a reference of the internal clock that sequences the other signals.
Figure 5-85. LCD Raster-Mode Control Signal Deactivation
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Peripheral Information and Timings
207
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