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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
R_SU
(0−31)
1
R_HOLD
(1−15)
R_STROBE
(1−63)
2
CS_DELAY
(0−3)
3
LCD_MEMORY_CLK
(MCLK) Sync Mode
19
6
6
LCD_MEMORY_CLK
(CS1) Async Mode
7
16
14
15
17
LCD_DATA[15:0]
Read
Status
18
6
6
8
LCD_AC_BIAS_EN
(CS0)
7
8
LCD_VSYNC
(ALE)
9
LCD_HSYNC
(WS)
12
12
LCD_PCLK
(RS)
13
A. Intel mode can be configured to perform asynchronous operations or synchronous operations. When configured in
asynchronous mode, LCD_MEMORY_CLK is not required, so it performs the CS1 function. When configured in
synchronous mode, LCD_MEMORY_CLK performs the MCLK function. LCD_MEMORY_CLK is also shown as a
reference of the internal clock that sequences the other signals.
Figure 5-80. Micro-Interface Graphic Display Intel Status
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
201
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